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As far as I know, a latch and a flip-flop are the same excepting that flip-flop only "works" with an edge of the clock (let's supose rising edge for the question.)

To make the flip-flop "work" only with a rising edge, we need a rising-edge detector:

enter image description here

So, as far as I know, a flip-flop is equal to a rising edge detector + a latch.

But my question is: Imagine a CPU with lots of flip-flops. Do all those flip-flops have an own rising edge detector inside of them, or there is only one rising-edge detector shared by all the flip-flops?

I mean, this is the typical "external" image of a D flip-flop:

enter image description here

Where you can see that the signal that is arriving is the clock (CLK), and this makes me think that ALL the flip flops in a CPU have their "rising edge detector" inside of them. But on the other hand I think that this cannot be possible! Because, why would they replicate a rising edge detector for each of the flip-flops they have, when they can save money and space by creating a single edge detector shared by all flip-flops?

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  • \$\begingroup\$ Maybe this answer will help you - electronics.stackexchange.com/a/473872/61398? \$\endgroup\$ – Circuit fantasist Jun 29 at 13:33
  • \$\begingroup\$ I finally understood, thank you :) And do you know if CPU's flip-flops implement this? Or do they implement master-slave flip-flops? \$\endgroup\$ – isma Jun 29 at 14:32
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    \$\begingroup\$ No, the schematic in the linked answer is not the way flip-flops are actually implemented in CPUs. Modern CPUs use CMOS transimission gates and inverters to built latches, then flip-flops. \$\endgroup\$ – Elliot Alderson Jun 29 at 19:57
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    \$\begingroup\$ No, a much more efficient design is used. For a simple example see play-hookey.com/digital/alt_flip_flops/cmos_d_flip-flop.html \$\endgroup\$ – Elliot Alderson Jun 29 at 20:20
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    \$\begingroup\$ This is a pretty standard flip-flop design for any CMOS digital circuit, CPU or microcontroller. However, high performance CPUs may use dynamic flip-flops which are even smaller than the design that I linked. This is a broad topic...you need to find a good book on CMOS VLSI design. One author I like is Weste. \$\endgroup\$ – Elliot Alderson Jun 29 at 21:01
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Each digital circuit can only work with a given amount of capacitance load which is given by the logical effort and its fan-out. If you connect too many blocks (latches in your case) at the output of the same rising edge detector, it would not work properly and would lead to lot of setup or hold violations after synthesis. The reason is you need to drive too much capacitance and the transistor drive is not strong enough to charge the node to VDD or VSS within the clock period, violating the static discipline. Thus you cannot use same rising edge detector for "a lot" of flip-flops.
There are different ways to implement flip-flops. The way you mentioned is just one of the many. The rising edge detector creates a "narrow" pulse around the rising edge of the clock and consequently enabling the latch only for the on cycle of the pulse. By narrow, I mean pulse width much smaller than the clock period. You can imagine as the clock speeds increase, it gets very difficult to get this narrow pulse. Hence, this technique is not used in usual implementation of the flip flop.
Instead, the static flip-flops are most commonly implemented using Master-Slave latches, connected in series, which work on the different levels of the input clock. For instance, rising edge Flip-Flop can be created if the Master latch gets enabled by digital 0 and slave latch is enabled by digital 1.
For even faster Flip-Flops, dynamic logic circuits like Strong-Arm latches can be used.

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Latches and flip-flops are not the same, but there are some controversy about the naming, so it is better always check, before making important design decisions based on them.

Latch has a transparent state and a lacthed state, when the output does not change. This is done by a level sensitive input.

Flip-flops are edge triggered for either rising or falling edge. They are created by a serial connection of two latches with inverted latching inputs. The first stage is called master, which samples the input during an edge, and holds it, while the second latch processes it. Always only one of the stages are transparent at any time, and the output changes only at dedicated edges of the clock. This operation itself does the edge detection. There is no dedicated circuitry which is responsible for detecting an edge.

There is usually no global clock due to the different delays in different clock paths, but local circuitry are synchronized with edge triggered flipflops, and the data processing within such a block might be combinational (i.e. combination clock-less digital standard cells), or it could use a different clock with a higher frequency in some cases. This might be similar to the hypothetical edge-detector you wrote in the original post, but it is fundamentally different in the sense, that it does not have enabling function; it simply does not let the input signal change until a specified clock edge.

Cutting-edge CPU design might be slightly different than usual digital circuit design. There some part of the circuit might be designed more in analog-like mindset, where the signal values are continuous rather than binary with some dealys. This is also to be considered when you read about the digital or processor design.

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