In my testbench i set reset=1 and then reset=0 after 1 ns In the simulation, err_count <= std_logic_vector(err_count_int); does not execute, does anyone know why? reset_out <= '1'; is also executed

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity controller is
            enable : in std_logic:='0';
            reset: in std_logic:='0';
            clk : in std_logic;
            eds: in std_logic:='0';
            ecs: out std_logic:='0';
            reset_out: out std_logic:='0';
            en_pipeline: out std_logic:='0';
            err_count: out std_logic_vector(4 downto 0)
end controller;

architecture beh of controller is

    signal err_count_int: unsigned(4 downto 0);
    signal increment: std_logic_vector(4 downto 0):= "00001";

    process(reset) begin
        if reset = '1' then 
            err_count_int <= to_unsigned (0, err_count_int'length);
            err_count <= std_logic_vector(err_count_int);
            reset_out <= '1';
        elsif reset = '0' then
            reset_out <= '0';
        end if;
    end process;
    -- process(clk) begin
        -- if enable = '1' and rising_edge(clk) then
            -- en_pipeline <= '1';
            -- err_count_int <= err_count_int + unsigned(increment);
            -- err_count <= std_logic_vector(err_count_int);
        -- elsif rising_edge(clk) AND eds = '1' then
            -- err_count_int <= err_count_int + 1;
            -- err_count <= std_logic_vector(err_count_int);
            -- ecs <= '1';
        -- end if;
    -- end process;
end beh;

  • \$\begingroup\$ Note that there is an all keyword that should be supported by all newer simulators that would eliminate this problem. \$\endgroup\$
    – po.pe
    Jun 30, 2020 at 5:50
  • \$\begingroup\$ Does the sensitivity list mean that only operations on those signals in the sensivity list is possible upon any changes to the sensitivity list? \$\endgroup\$ Jun 30, 2020 at 12:22
  • \$\begingroup\$ Or does it simply mean when any signal in the sensitivity list changes, all statement in the process are evaluated and executed? \$\endgroup\$ Jun 30, 2020 at 12:23
  • 1
    \$\begingroup\$ The sensitivity list tells the simulator which signal changes trigger a new evaluation of the process. \$\endgroup\$
    – po.pe
    Jun 30, 2020 at 14:12
  • \$\begingroup\$ The thing to note here is that although this is how simulation works, it is not necessarily how a synthesized design will work. Using the "all" keyword is the safest option but potentially could slow down certain simulations. \$\endgroup\$
    – ks0ze
    Jun 30, 2020 at 18:52

1 Answer 1


You are missing err_count_int in your sensitivity list. Basically, a sensitivity list says "only perform calculations (in the simulation) when one of these signals changes".

Therefore, reset changes to 1 and you essentially simultaneously set err_count_int, err_count, and reset_out. But, the updated version of err_count_int isn't ready yet so I'm assuming you are getting undefined output for err_count. reset_out gets set correctly because the constant '1' is always available for assignment.

If you need further explanation, please also post the testbench and your simulation results.

  • \$\begingroup\$ But why when im using process(clk) begin with exact same assignment statements it works? \$\endgroup\$ Jun 30, 2020 at 12:21
  • \$\begingroup\$ @MarkHenderson, could you edit your question to include a simulation output and testbench? Making that change, you're telling the simulator to perform calculations based on a signal that is not part of the process. This will lead to mismatches between hardware and simulation and should not be done. The simulation calculation will be updated every rising/falling edge of clk, so I could see err_count being correct after a rising and falling edge. \$\endgroup\$
    – ks0ze
    Jun 30, 2020 at 13:09

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