What are some proven and effective ways to reduce overall power consumption of a given circuit?

Things like:

  1. Choose efficient, modern components;
  2. Use high-efficiency components over lower-efficiency equivalents (at possibly higher cost)
  3. Don't overbuild: if a design calls for an indicator light of a given brightness, don't exceed the spec
  4. Take advantage of the sleep function of a microcontroller.

Are excluded, because they should be a given. I'm looking for slightly less obvious ways, or "tricks" that professionals have used when power is precious (like on a satellite or rover). Also, design changes like going from direct-driving a quantity of LED's to multiplexing them instead.

  • \$\begingroup\$ This is way too broad of a question. It depends on the specifics but in general, just having your board powered off saves a lot of energy (and then there is still some battery self discharge). So just eliminate the circuit and there you go. \$\endgroup\$ – Gustavo Litovsky Dec 7 '12 at 18:51
  • \$\begingroup\$ Please provide details of your circuit and then we can help \$\endgroup\$ – Gustavo Litovsky Dec 7 '12 at 18:57
  • \$\begingroup\$ 5) Turn the power off on components you don't need all the time. \$\endgroup\$ – kenny Dec 7 '12 at 19:14
  • 1
    \$\begingroup\$ 6) quick pulse LEDs >30hz rather than on/off \$\endgroup\$ – kenny Dec 7 '12 at 19:15
  • \$\begingroup\$ This isn't about a specific circuit. Perhaps it's simply too broad. \$\endgroup\$ – JYelton Dec 7 '12 at 19:28

This won't cover everything but it's a start:

In electronic circuits wasted power mostly goes to heat and some to em radiation. To reduce power consumption you would:

  • reduce heat generation
  • reduce emissions

The largest heat generation occurs when you have a voltage drop and some current of significance. For example, a voltage regulator mainly dumps the excess voltage x current as heat. So avoid places where you have to treat power by throwing the excess away. This also applies to power supplies.

POWER CONVERSION: If you have DC to DC conversion using a switchmode supply, make sure it's the highest efficiency you can build/get. Generally, BJT transistors run hotter than MOSFETs, so you should be looking at a synchronous switch mode supplier that utilizes MOSFET/CMOS technology not Biplolar. Also, take a look at the diode specs and chose ones that have a lower drop. By replacing the transistors and diodes on one design we were able to go from 50% efficiency range to high 80%. On a circuit, you can typically pick out culprits if you aim a Thermal Imaging camera at the circuit and look for hot spots.

EM and RADIO if your board is noisy enough to waste power due to em emissions you've probably got more issues, however good power management (decoupling caps/filters) can lead to less noise and more efficiency. Sometimes, you can't help it, if there is a receive/transmit antenna and the "RF GUY" says it's as good as it gets (see iPhone GPS receiver) then you know where some of the power is ending up. Making reception more efficient might be more bang for buck since most devices receive more than transmit.

CLOCK CYCLE and RAM if you have a 32bit ram running at 100Mhz, every time each of those data bit lines switch between 1 and 0 you dump a bit of power out and it could wreak havoc on a badly designed board. reducing the capacitance of each data bus line, proper termination, make a difference. Even though CMOS technology has pf's of capacitance and mega ohms of resistance, (megs and puffs they say) every time they switch, you lose the charge. Your 3Ghz intel processor is doing 37 Watts worth of that. So shut down the parts of the chip you're not using and put the darn thing to sleep as often as possible.

Passive Components Here you want to generally lower resistance of anything that has current going through it: Choosing better capacitors (lower ESR) in high speed circuits is another practice. As frequency rises the resistance of even an X7R cap will start looking mad (resistance ->heat). Similar treat goes for choosing inductor values. if You can, have a power layer and a ground layer with less than 0.008" prepeg in between. This creates a nice low resistance capacitor at higher speeds. You'll need a minimum of 1 square inch for this to be of any significance.

Asymmetric Crystal Caps the crystal used to for generating clock signals usually spec some capacitance (say 12.5pf) and most people simply put 2 of 25pf and move on. Making this asymmetric such as a 22 and 33 -> ~13pf will run the crystal and save long term power.

beyond that, you could go pedantic and look at PCB material, placement of traces and trace patterns to lower resistance, etc. I've heard of a satellite circuit design advisor saying:

"now, rotate this part 90 degrees and it'll then work in space". (I believe the junoir guy had an L shape trace -> single pole antenna :)

  • \$\begingroup\$ @ eg. 100MHz RAM => decrease clock frequency of the circuit. You often don't need high clock speeds anyway. \$\endgroup\$ – jippie Dec 7 '12 at 20:53
  • \$\begingroup\$ Can you elaborate on Asymmetric Crystal Caps? I mean is it just the 0.5 pF difference you're aiming at? \$\endgroup\$ – jippie Dec 7 '12 at 20:57
  • \$\begingroup\$ @jippe yes, the fewer the switches (clock cycle), the lower the consumption. For the crystal loading caps, you want two different valued capacitors (e.g. 22pf and 33pf) as opposed to the same value capacitors people place twice(25pf) for economic reasons. The 0.5pf in this example: 22pf and 33pf are popular values and the crystal will still resonate albeit slightly slower or faster subject to your tolerance (this is how you can tune/shift the crystal for a specific circuit). Remember the load value is in series: 12.5pf = c1*c2/(c1+c2) \$\endgroup\$ – MandoMando Dec 7 '12 at 22:45
  • \$\begingroup\$ An interesting technique for reducing DRAM refresh energy is to recognize that not all DRAM cells have the same refresh requirements and the DRAMs are spec'ed by the worst case. If one can sacrifice a small fraction of capacity, the refresh rate can be greatly reduced. E.g., see "Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM" (Venkatesan et al., 2006) \$\endgroup\$ – Paul A. Clayton Dec 8 '12 at 0:27
  • \$\begingroup\$ @PaulA.Clayton: Thank you. that's a fascinating paper. \$\endgroup\$ – davidcary Dec 8 '12 at 13:45

Not the answer you're looking for? Browse other questions tagged or ask your own question.