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I a need 2 units of 2-to-1 selector/multiplexer functions on a crammed board, ideally with a single DIP-14 or -16 chip. Looking around for something I found this formula

(S nand A) nand ((not S) nand B)

which is great, as I can build it with a single 74LS00 quad NAND gate chip as:

(S nand A) nand ((S nand S) nand B)

So I know I can do it with two DIP-14 chips. But I want only one!

Truth table:

S A B|Y
-----+-
L L x|L
L H x|H
H x L|L
H x H|H

or fully expanded sorted by binary value of S,A,B:

S A B|Y
-----+-
L L L|L
L L H|L
L H L|H
L H H|H
H L L|L
H L H|H
H H L|L
H H H|H

or fully expanded sorted by Y

S A B|Y
-----+-
L L L|L
L L H|L
H L L|L
H H L|L
L H L|H
L H H|H
H L H|H
H H H|H

I tried a combination of two NAND or two NOR gates also don't work. None gives a L L L -> L or H H H -> H.

A standard AND-OR-invert (AOI) gate also doesn't work as nothing gets any L L L L -> L or H H H H -> H. The 2-2 AOI gate will always output 0 if three or all four inputs are 1, and 1 if three or all four inputs are 0. Same problem with and OAI gate.

For a moment I thought the double XOR combination suggested in Can I simplify this to a 2-to-1 multiplexer? was going to do it, which would have been so nice as I could have built two with one chip, but then it doesn't work. It seems so close though!

Maybe I should say what I am really ultimately trying to do: I use 74LS161 counters (or any TTL counters) as registers, 4 bits (one nybble) each, and I have two such counters chained together where the ripple carry out of the low nybble connects to the clock of the high nybble. I want to be able to synchronously preset either one independently. Easy to do for the low nybble, not so easy for the high nybble as the synchronous load happens on the rising clock edge, and the clock for the high nybble is connected to the ripple carry output.

So I figured a selector should be doing it, but the 74' series only has quad 2-to-1 selector/multiplexer with a single selector, but I need two independent selectors!

Any trick? Perhaps a counter which can be synchronously pre-set but has a different ripple clock input from the clock edge that triggers the pre-loading? That's really all I want. Oh boy, if it could also be three-state it would be perfect. But none such exists. That's why I am so short on space already.

UPDATE: the comments asked if I could show schematics, if you will excuse my hand drawn one, for this circuit drawing tool isn't good with ICs.

enter image description here

Dave Tweed had provided the final clue in the comment, so that answers it. But in correct StackExchange-iquette, I put the answer into a separate ... answer ... [drumroll ...]

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  • \$\begingroup\$ From your title alone, I'm not sure about why the 74157/74158 isn't appropriate. I probably need to read more closely, below. \$\endgroup\$ – jonk Jul 1 '20 at 1:22
  • \$\begingroup\$ "it should be as fast as possible" - why? \$\endgroup\$ – Bruce Abbott Jul 1 '20 at 1:40
  • \$\begingroup\$ @BruceAbbott sorry that is not really important, I put it in parentheses. Might even delete it. \$\endgroup\$ – Gunther Schadow Jul 1 '20 at 1:50
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    \$\begingroup\$ "ripple carry out of the low nybble connects to the clock of the high nybble." - why are you doing it this way when the counters can be chained synchronously? Can you show us the circuit? \$\endgroup\$ – Bruce Abbott Jul 1 '20 at 1:56
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    \$\begingroup\$ "clock for the high nybble is connected to the ripple carry output." Why did you do it that way? That makes it a kind of hybrid synchronous/ripple counter. There is a way to build a fully synchronous 8-bit counter with a common clock for both chips, using the ENP and ENT inputs. Read the datasheet. \$\endgroup\$ – Dave Tweed Jul 1 '20 at 1:56
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OK Dave Tweed should really get the credits for solving my problem. He said to read the fine data sheet where a synchronous chaining of counters is provided, which are all connected to the same main clock, and the ripple carry connects to the ENT pin.

enter image description here

This really solved my whole practical problem.

Also, in good StackExchange-iquette I must rant a little bit about the confused question, which is making the mistake to try to find a specific solution, the 2-to-1 selector gating, rather than starting from the actual goal, the counter issue.

Meanwhile, I still found it interesting to figure out a way to combine the the basic logic gates to make a selector, and that the easiest solution that avoids mixing 3 types of gates is to use 4 NAND gates -- of course, you can do everything with only NAND -- but that probably there is no simpler solution to a 2-to-1 line selector than 4 NANDs if you want to avioid mixing of gate types.

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Try MC4052 type of multiplexors. Intended for "analog" but the on_resistance may be low enough.

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