I am new to layout designing. I am using Eagle 9.5. Here is the layout design of my project:

enter image description here

Right section of the PCB is for analog circuit. middle section is for DAC and ADC and digital output of those two ICs are going to two of the long pin headers. There are two analog switch ICs which are controlled by SPI and they are in the analog section but it will be active only when there is no analog signal present. (switch will select certain resistor and capacitor for gain setting and compensation respectively). left side of the PCB for power supply. whole board will sit on Atmega development board.

I am using 4 layer board and layer stack are: top: signal 2nd layer: power supply (it's not a plane but thick traces)
3rd layer: signal layer
bottom layer: ground plane. Analog signal frequency: 1-100khz
Digital signal frequency: upto 18Mhz
Analog and digital signals doesn't overlap on DGND and AGND plane (there are few exceptions)

I have a question about return-path/ground. I read few documents to understand how signal current will return and accordingly I have designed the ground plane. image of bottom layer:
enter image description here

My colleague told me that there will be potential difference between PGND in bottom layer and AGND of analog section and it is not good for the design but my understanding is that if I have intact ground plane then it will not be any potential difference. it only happens when I share ground trace with multiple components and then connect to ground plane. like this:
enter image description here

Please tell me, is my colleague correct or my ground plane is alright?

EDIT : here is my load which is connected to the virtual ground of the trans-impedance amplifier. load is basically electrochemistry cell. it might not draw any current. Because of reaction in the cell it may generate few nano amperes to milli amperes.

Basically, I am implementing signal processing for impedance spectroscopy. few hundreds of millivolt signal is given to the load as a excitation signal which will be pure sine wave with dc offset. so, range of the signal could be -2.5v to +2.5V

enter image description here

  • \$\begingroup\$ I see three connections between AGND and DGND - this seems problematic but the PGND doesn't. \$\endgroup\$
    – Andy aka
    Jul 1, 2020 at 15:23
  • \$\begingroup\$ I have edited bottom layer image to show AGND and DGND connection. 1st and 4th connection is for digital traces which gois to analog switches and it will be active when analog section is not working. 2 and 3 connection is under mixed signal ics. do you still think is it a problem? \$\endgroup\$ Jul 1, 2020 at 16:06
  • \$\begingroup\$ Do you have an isolated design? What is the gain on the analog section? What level of signal are you amplifying (IE uV or mV)? \$\endgroup\$
    – Voltage Spike
    Jul 1, 2020 at 16:09
  • \$\begingroup\$ The ground plane "fence" doesn't really do much, just routes all the currents on the ground plane through 4 points. \$\endgroup\$
    – Voltage Spike
    Jul 1, 2020 at 16:12
  • \$\begingroup\$ I am converting current to voltage. current could be from few hundreds of nano-amps to few miliamps. so feedback resistor of transimpedance amplifier goes upto 1Mohms. I also have 2nd stage amplifier whose input would be in millivolts and amplify to few volts. amplifiers vcc is -2.5 and +2.5 v. \$\endgroup\$ Jul 1, 2020 at 16:41

2 Answers 2


My colleague told me that there will be potential difference between PGND in bottom layer and AGND of analog section and it is not good for the design but my understanding is that if I have intact ground plane then it will not be any potential difference.

There will be a potential difference, if the ground plane was made from a superconductor, then there would be negligible potential difference. All materials have resistance.

Ground planes can be imagined like a grid of resistors:

enter image description here
Source: https://www.mathpages.com/home/kmath668/kmath668.htm

This means that any current from point to point on the ground plane will generate a voltage, but it will be very small. 1oz copper has a resistance value of 0.5mΩ/square inch. The value of the voltage that the ground will change still follows V=I*R but the problem is with the resistor "grid" (which actually is continuous) currents are 2 dimensional. In the image below lets suppose the point Vb is a higher voltage than Va, current will flow in all resistors, but higher in the ones between Vb and Va. Now imagine the resistors are a continuous piece of 1oz copper, and the points are vias.

enter image description here
Source: https://rosettacode.org/wiki/Resistor_mesh (modified by me)

The amount of voltage that will be generated by currents can be estimated, with 0.5mΩ of resistance per square inch, 1mA of current would generate ~5uV of voltage on the ground plane.

In analog designs, a designer needs to first consider if ground plane effects will really be a problem (if your design is on the uV or nV level, then it will).

If it does, then currents will need to be reduced with isolation OR by proper component placement. Currents will always follow the lowest impedance (or for DC lowest resistance) path back to their source. If you have a load that sends a lot of current through the ground plane, it can cause sensitive analog electronics to see the ground change, which contributes to noise and error in the signal.

So your diagram actually looks like this: enter image description here

And Rg could have other currents flowing through it from other components. From the diagrams above, I cannot tell exactly what these would be, it requires a schematic and usually a good look at the CAD and a knowledge of all the currents and the locations of these on the PCB.

  • \$\begingroup\$ thanks for the detailed explanation. I have edited my post to give basic information about load. I think I don't have consider ground plane effect. could you please comment on my edit? \$\endgroup\$ Jul 1, 2020 at 16:35
  • \$\begingroup\$ What is the gain resistor on the OP07? \$\endgroup\$
    – Voltage Spike
    Jul 1, 2020 at 16:40
  • \$\begingroup\$ I am not actually using OP07 it was just to show how load is connected. So gain resistors for Transimpedance amp are 100, 1k, 10k, 100k, 1M. And on second stage of gain where using normal opamp whose gain resistors are 1k, 10k, 50k, 100k. All these resistors will be selected by analog switches. \$\endgroup\$ Jul 1, 2020 at 17:01
  • \$\begingroup\$ Your going to need a guard trace if you want to amplify nA, at that level leakage from the PCB can become a problem. Is this for an ion meter probe? The opamp will also need a lower input bias current than the meter. \$\endgroup\$
    – Voltage Spike
    Jul 1, 2020 at 17:04
  • \$\begingroup\$ I was skeptical about whether to guard high impedance signal or not because Output impedance of the electrochemistry cell will not be in teraohms hence leakage current probably will not matter (?)Therefore I didn't add it into the design. But I can manage to put guard ring in layout. I am not using ionmeter. So input to the TIA will be directly from electrochemistry cell. I am using ADA4530 as a TIA. It requires bias current in few fAmps. \$\endgroup\$ Jul 2, 2020 at 5:09

Some contributions in addition to the excellent writing of VoltagSpike.

  • current follow ALL paths, proportional to the conductance; you can count the # of squares (each resistor grid is a square) in various paths from B to A, and compute the resistance of each path; realize a viable path is the current creeping around the edge of the PCB --- that path may be 3X or 4X longer than the direct path between B and A, but there are numerous paths that are longer than the direct path, and you should include all those; don't worry about exactness, just draw approximately equally spaced paths, as shown in the diagram; if you can use most of the squares in your loops, you are good.

  • the voltage drop of 0.000500 ohm and 1milliAmp is 0.5 microVolts, which may or may not dominate your error budget; you do have an error budget, right? Ask your colleague for assistance on error budgets.


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