Positive edge detection triggers on negative edge too

Question

I have 74LS170s and 74LS670 register files which have the trouble that they are not edge triggered but like SRAM accept data for the entire duration of the write gate being low.

So, I have the following circuit:

^{simulate this circuit – Schematic created using CircuitLab}

The idea is the capacitor should pulse quickly high on the positive clock edge, that is then inverted (I actually use a 74LS14 Schmitt-trigger inverter) which gives me a negative pulse on the rising edge of the clock, just what I need to combine it through an OR gate with the active-low !LOAD signal, like the one you'd put on the 74LS173. And I plan to do the single OR gate with just a couple of diodes and a resister, as I don't want to deploy 74LS32 chips everywhere I need this pulse.

However, as you can see here, the circuit produces a second little pulse on the falling edge of the clock. It's quicker, but it's a spike that could badly interfere with the functioning of that register. This is measured right after the inverter, it's not about the OR gate.

What am I doing wrong? How can I get rid of this second pulse?

Answer 1

You are driving the 74LS14 input below ground, which is outside of the normal operating region.

Try connecting a diode (preferably a Schottky type such as BAT54) between the input and ground so that the input cannot go much below ground. A 1N4148 may work.

Answer 2

Most SRAM are also level triggered, few are edge triggered.

One technique of making an SRAM or register file appear edge-triggered is to put a latch (eg LS373) in front of the register file with the latch fed the opposite polarity clock.

With your circuit for creating a pulse you are injecting a large current into the substrate of the inverter on the falling edge of the input signal - this can have all sorts of undesirable effects, it is probably causing the issue you are seeing.

As mentioned by Spehro a diode may avoid this problem but it is better to design the circuit to not do this current injection.

A common way to reliably create an edge pulse from a signal is by combining a signal with a delayed version of itself. This is much more reliable than differentiating the signal. The pulse width can be increased by increasing the RC delay in front of the inverter. With just an inverter the pulse width will be about one gate delay - 5-10ns.

Answer 3

Answer by Spehro Pefhany was spot on for this issue of the second dip. I just took some diode I happen to have, 1N4002, hooked it from GND to the inverter input pin, and it turned the spike into a mere wiggle. I just add this as a reply so I can confirm the answer with proof.

[EDIT: I must be honest that I also switched out the Schmitt inverter with the non Schmitt. Today I have seen more of that spike again. But need to get a Schottky diode first to see if it gets better.]

Unfortunately this has moved the problem from one of a second dip to one of being unable to make the dip brief enough that it really clocks in the momentary value before the input value (on the bus) changes right after the rising edge.

This here was taken with that 10 nF capacitor, that is probably too long. I tried smaller values and it's very tricky, either I get a pulse that's not noticed by this register file chip (too short) or it is too long, or maybe too late.