I have 74LS170s and 74LS670 register files which have the trouble that they are not edge triggered but like SRAM accept data for the entire duration of the write gate being low.
So, I have the following circuit:
The idea is the capacitor should pulse quickly high on the positive clock edge, that is then inverted (I actually use a 74LS14 Schmitt-trigger inverter) which gives me a negative pulse on the rising edge of the clock, just what I need to combine it through an OR gate with the active-low !LOAD signal, like the one you'd put on the 74LS173. And I plan to do the single OR gate with just a couple of diodes and a resister, as I don't want to deploy 74LS32 chips everywhere I need this pulse.
However, as you can see here, the circuit produces a second little pulse on the falling edge of the clock. It's quicker, but it's a spike that could badly interfere with the functioning of that register. This is measured right after the inverter, it's not about the OR gate.
What am I doing wrong? How can I get rid of this second pulse?