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I read this statement in a textbook on VLSI design:

Parallel divider use combinational circuits only, thus faster in operation than serial one, which has less hardware equipment

Here a serial divider is a sequential circuit which performs an operation repeatedly to get the result. Parallel divider is a purely combinational composed of full subtractors and multiplexers.

Why are the serial dividers slower than parallel dividers? Since the integrated circuit of a serial divider is smaller, I thought that the time taken for a signal to reach from one end to another should be lesser.

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    \$\begingroup\$ You are thinking of clock speed, which may not be the same as latency or throughput. Smaller silicon means you can run it on a faster clock, but the fact it is re-using logic means it takes multiple clock cycles to generate an output. \$\endgroup\$ – DKNguyen Jul 7 '20 at 3:39
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    \$\begingroup\$ Serial != pipelined. Two entirely different concepts. In general pipelined IS parallel, just broken up into smaller steps by pipeline registers. \$\endgroup\$ – Dave Tweed Jul 7 '20 at 3:40
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    \$\begingroup\$ @DaveTweed Hmmmm....yes. Sounds like the OP is talking about the same stage being used multiple times for similar operation to generate a result (serial) rather than having a chain of logic that is passed on every clock cycle (pipelined), which has long latency but shouldn't change throughput. \$\endgroup\$ – DKNguyen Jul 7 '20 at 3:43
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    \$\begingroup\$ @DKNguyen: Yes, pipelining generally increases latency, but in exchange, you get greatly improved throughput -- a result on every clock -- because the clock can be so much faster. That's the whole point! \$\endgroup\$ – Dave Tweed Jul 7 '20 at 3:48
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    \$\begingroup\$ Responding to edit ... "speed" is a vague term -- it could mean either low latency or high throughput, but not both, as we just discussed above. Which do you mean? In my case, I need the throughput (150 million results per second in an FPGA), so I'm designing a pipelined divider. \$\endgroup\$ – Dave Tweed Jul 7 '20 at 3:53
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Both?

The throughput/latency trade is important, because it gives you two different definitions of "speed" to work towards. Do you want to pass in A/B and get the result as fast as possible? Or do you have two huge sets of numbers (A1, A2, .. A1000) (B1 ... B1000) and want to get the whole lot done in as short a time as possible? Because the answers are subtly different.

Division is different from the other primitive operations in that most of the algorithms are inherently iterative - if you were doing it on paper, you'd be doing the same thing multiple times on intermediate results. So dividers tend to be multi-cycle anyway.

Note that with pipelined architectures, while they tend to have a higher clock speed they also tend to take more cycles to give back the answer, so the overall time many not be shorter.

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