4
\$\begingroup\$

Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says (emphasis mine):

Timing Budget

Suggested practice is to look at the design from a timing budget standpoint to provide flexibility in the routing portion of the design, if there is suitable margin. This starts with simulation. By referencing the eye diagrams in this document, a setup and hold time can be established. From here, the parameters not included in the simulation must be added. Typical routing for DDR4 components requires two internal signal layers, two surface signal layers, and four other layers ( 2 VDD and 2 VSS) as solid reference planes. DDR4 memories have VDD and VDDQ pins, which are both typically tied to the PCB VDD plane. Likewise, component VSS and VSSQ pins are tied to the PCB VSS plane. Each plane provides a low-impedance path to the memory devices to deliver VSSQ. Sharing a single plane for both power and ground does not provide strong signal referencing. With careful design, it is possible for a split-plane design to work adequately:

  • Designs should reference data bus signals to VSS.
  • CA bus and clock should reference VDD.
  • Signals should never reference VPP.

Why Command, Address bus and clock should reference VDD?

I think the language on the paragraph is a bit ambiguous, some people understand that we SHOULD, but I think its saying what to do IF you have to split a plane...but still looking into DDR4 RAM modules PCBs I can see it's splitted:

RAM

\$\endgroup\$
4
  • \$\begingroup\$ need to get more data, but from my experience we never reference control/clock nets to VDD. all are referenced to GND. \$\endgroup\$ – user19579 Jul 7 '20 at 10:02
  • \$\begingroup\$ I added the whole section from the Techincal Note. I know that in theory power and ground planes can act as return planes for high-speed signals, but I have never seen an explicit recommendation for it. \$\endgroup\$ – mFeinstein Jul 7 '20 at 20:22
  • \$\begingroup\$ I have no experience with this and could be talking out my ass, but I feel that recommendation is specifically to accommodate limitations in the suggested stackup. Without using the Vdd as a reference plane, you throw away two of the signal layers. I'm guessing they just want the clock to be on a separate layer or reference a different plane than the clock signals and prioritized them. \$\endgroup\$ – DKNguyen Jul 7 '20 at 20:57
  • \$\begingroup\$ The problem I see is the language...it makes sense to say "if you have to reference something to VDD, so reference the Address, Control and Clock signals, s those have half the frequency as the Data lines"... but the actual language sounds more as a standard. \$\endgroup\$ – mFeinstein Jul 7 '20 at 21:00

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.