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When I try to the code below, program running very well. But when I enable PLL_ON bit, the program does not work.

Code that works:

void SysClockConfig()
{
    RCC->CR = 0x00010000;               // HSE ON
    while(!(RCC->CR & 0x00020000));     // HSE READY
    RCC->CR |= 0x00080000;              // CSS ON
    RCC->PLLCFGR |= 0x04402D04;         // P Q N M SETTINGS
    RCC->CFGR |= 0x0009402;             // APB SETTINGS
    RCC->CIR = 0x00880000;
    RCC->AHB1ENR |= 0x000007FF;         // GPIOs ARE ENABLE
}

void GPIO_Config()
{
    GPIOG->MODER = 0x14000000;              // GPIOG 13-14 ARE OUTPUT
    GPIOA->MODER = 0x00000000;              // GPIOA IS INPUT
    GPIOG->OTYPER = 0x00000000;             // PUSH-PULL
    GPIOG->OSPEEDR = 0x3C000000;            // HIGH-SPEED OUTPUT
    GPIOG->PUPDR = 0x14000000;              // PULL-DOWN
}

Code that does not work:

void SysClockConfig()
{
    RCC->CR = 0x00010000;                           // HSE ON
    while(!(RCC->CR & 0x00020000));     // HSE READY
    RCC->CR |= 0x00080000;                      // CSS ON
    RCC->PLLCFGR |= 0x04402D04;       // P Q N M SETTINGS
    RCC->CR |= RCC_CR_PLLON;                        // MAIN PLL ON
    while((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);      // MAIN PLL LOCKED
    RCC->CFGR &= ~RCC_CFGR_SW;  
    RCC->CFGR |= RCC_CFGR_SW_PLL; 

    while((RCC->CFGR & RCC_CFGR_SW_PLL) != RCC_CFGR_SW_PLL);
    RCC->CFGR |= 0x0009402;           // APB SETTINGS
    RCC->CIR = 0x00880000;
    RCC->AHB1ENR |= 0x000007FF;       // GPIOs ARE ENABLE
}

void GPIO_Config()
{
    GPIOG->MODER = 0x14000000;              // GPIOG 13-14 ARE OUTPUT
    GPIOA->MODER = 0x00000000;              // GPIOA IS INPUT
    GPIOG->OTYPER = 0x00000000;             // PUSH-PULL
    GPIOG->OSPEEDR = 0x3C000000;            // HIGH-SPEED OUTPUT
    GPIOG->PUPDR = 0x14000000;              // PULL-DOWN
}
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  • \$\begingroup\$ When you say that, the code doesn't work, have you checked that the two while loops are not stuck in infinite loop ? How much of the program gets executed in the code that does not work ? \$\endgroup\$
    – AJN
    Jul 7, 2020 at 12:58
  • \$\begingroup\$ Try an official example first, then compare in detail what it's doing deep in the library code to what you are doing by hand with raw values. Also note this gets yet trickier if the PLL has already been used since reset, for example by a bootloader. \$\endgroup\$ Jul 7, 2020 at 13:37
  • \$\begingroup\$ How can I detect infinite loops by using Keil debugger? \$\endgroup\$ Jul 7, 2020 at 13:46
  • \$\begingroup\$ When I monitored by Keil debugger, I saw PLL has not already been used. I ran the program step by step and PLL_ON bit has been setted when the program execute the while loop. \$\endgroup\$ Jul 7, 2020 at 13:50

2 Answers 2

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I solved the problem by adding the code below. Thanks for all answers.

FLASH->ACR = FLASH_ACR_LATENCY_5WS /* 6 CPU cycle wait */ | FLASH_ACR_PRFTEN /* enable prefetch */ | FLASH_ACR_ICEN /* instruction cache enable */ | FLASH_ACR_DCEN; /* data cache enable */
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You've enabled the HSE, and you're using it as the PLL source (RCC->PLLCFGR.PLLSRC).
So What is your HSE crystal frequency?

You need to make sure that your PLL configuration obeys all of the max/min frequency limits of the device.
The input to the PLL must be in the range of 1MHz to 2MHz, so with your configuration where you have have the initial PLL M divisor set to 4 (RCC->PLLCFGR.PLLM bits), your HSE crystal frequency must be between 4MHz and 8MHz - is it?

If it's 8MHz, then your PLL configuration would be OK, but you'd still need to increase the APB1 Prescaler (RCC->CFGR.PPRE1 bits) which you currently have set as /2 (PPRE1 == 4) to /4 (PPRE1 == 5).
An HSE frequency of 4MHz would work with your existing configuration.

I've based my assumptions & calculations on an STM32F429 device.
It's possible that you may have different max/min frequency values

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  • \$\begingroup\$ thanks for your answer. does not <code> RCC->CFGR |= RCC_CFGR_SW_PLL; </code> line set HSE as PLL source? You are right, I'm using STM32F429. \$\endgroup\$ Jul 7, 2020 at 14:52

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