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sorry it could be a basic question but still, I didn't find the answer on the web

is the SPI clock always active or active only when CS is low (during data exchange)?

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    \$\begingroup\$ It would be better to say that the SPI clock is irrelevant when /CS is not low. It might or might not be doing anything during such times; the device shouldn't care. \$\endgroup\$ – jasonharper Jul 8 '20 at 16:28
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The SPI clock is only active while the chip select is low, yes.

As correctly stated in the comment, if there's no transmission active, the clock will stay idle even if the chip select is low.

The idle state of the clock (high or low) depends on the chosen SPI mode

https://www.analog.com/media/en/analog-dialogue/volume-52/number-3/introduction-to-spi-interface.pdf

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    \$\begingroup\$ This answer suggests that clock is always active when chip select is low. No, clock is only active when master wants to send or receive data, so during byte transmissions. Chip select is irrelevant, as you might have ten chips with each having their own way of chip select, such as high when active, or for simple shift registers, a load pulse after transmission is done. \$\endgroup\$ – Justme Jul 8 '20 at 8:21
  • \$\begingroup\$ Agreed, I'll clarify \$\endgroup\$ – po.pe Jul 8 '20 at 8:30
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SPI is not some rigorously defined standard, but more of a de-facto thing.

Normally the SPI clock is only active when the master wants to send/receive data. In general a SPI transaction looks like.

  • The master asserts chip select
  • The master clocks through the desired number of data bits. Normally data is clocked out on one edge and clocked in on the other edge avoiding the need for highly precise timing between clock and data. Exactly which edges are used depends on the SPI "mode"
  • The master deassets chip select to end the transaction.

If you are designing a slave you should be aware that it's common for one master to drive multiple slaves with separate chip selects. So your slave must ignore any clock transitions that happen while it's chip select is not asserted. This of course in-turn means that a master could run the clock continuously (as long as it took care to observe the required timings between clock transitions and chip-select transitions).

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    \$\begingroup\$ Although because of the mentioned lack of standardization, lots of devices require fishy stuff like: idle time between /SS and clock/data, or extra clock pulses, or extra idle time between packages, or dummy data trains before MISO goes live etc etc. Also there's "daisy chain" but that's another story as well. \$\endgroup\$ – Lundin Jul 9 '20 at 6:39
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Data is clocked out of MOSI and into MISO when the clock is active, it's only driven when CS is low and there's a transaction happening.

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  • \$\begingroup\$ CS could be high if the master is sending data to a different chip! \$\endgroup\$ – user253751 Jul 8 '20 at 10:46
  • \$\begingroup\$ What I have is true from the masters perspective, but you’re right \$\endgroup\$ – Colin Jul 8 '20 at 10:47
  • \$\begingroup\$ Or if a chip has active high chip select. Or does not use a chip select at all. \$\endgroup\$ – Justme Jul 8 '20 at 11:14
  • \$\begingroup\$ @Colin there exists a SPI bus specification by Motorola? Please link to it? \$\endgroup\$ – Justme Jul 8 '20 at 11:53
  • \$\begingroup\$ @Justme I apologise, I'd made an assumption based on everything I've seen but it seems to be a de-facto standard, rather than anything official. \$\endgroup\$ – Colin Jul 8 '20 at 12:11
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While the other answers describe a common implementation, there is no requirement that the controller cease clocking when no controlled device is selected. Controlled devices must ignore the clock when not selected. The controller may continue to drive the clock but it need not do so.

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No. It is not active always, and it is not active when CS is low. It's active only when data is being transmitted.

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The SPI clock may or may not be always active. This is application dependent.

Example:

http://ww1.microchip.com/downloads/en/devicedoc/39699b.pdf

In the PIC24F Family Reference Manual 'SPI' chapter, it explains that the PIC24 series SPI channels support both a mode where the clock toggles only during data transmission, and a mode where the clock is continuously free-running.1

In Standard Master mode, the system clock is prescaled and then used as the serial clock. The prescaling is based on the settings in the PPRE1:PPRE0 (SPIxCON1<1:0>) and SPRE2:SPRE0 (SPIxCON1<4:2>) bits. The serial clock is output via the SCKx pin to slave devices. Clock pulses are only generated when there is data to be transmitted.

SCKx PIN IN FRAMED SPI MODES: When FRMEN = 1 and MSTEN = 1, the SCKx pin becomes an output and the SPIx clock at SCKx becomes a free-running clock. When FRMEN = 1 and MSTEN = 0, the SCKx pin becomes an input. The source clock provided to the SCKx pin is assumed to be a free-running clock.

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1 In either mode, the PIC can produce the clock itself (Master mode) or it can receive the clock from the peripheral (Slave mode). In either case, the !SSx pin determines whether any action is taken or not.

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Slave device can also control clock line, When a slave device is busy and the sametime master tries to send data to slave then the slave device pull down the clock line until it comes to idle.

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    \$\begingroup\$ The SPI clock is driven high and low, a slave device driving it low would cause contention, there’s clock stretching with I2C \$\endgroup\$ – Colin Jul 9 '20 at 7:16

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