You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°?
It is not possible to answer the question because it does not say what the waveform "f" is.
If f is a random digital waveform like bits on a data line, then the concept of "phase of f" does not apply to it.
If f is actually a periodic waveform, then the concept of "phase of f" would apply to it, and "180° phase" would mean to delay it by a number of clock cycles equal to half a period of f. But the question does not say what the period of f is, so it can't be answered.
If we upgrade the question to this:
a digital waveform f which changes only at every negative edge of the clock.
Then it can be answered, as f is now a periodic signal with 50% duty cycle, its frequency is half the clock frequency, and its edges are aligned with negative edges of the clock.
Well, acksually, it still can't be answered, because we don't know the setup/hold time. If comes out of a flop clocked on the negative edge, then f will change state just a bit after the negative edge, and if that can be fed as an input to a negative clocked flop without violating setup/hold timings, then the answer is a single negative clocked flop. Unless the inverter on the clock adds enough delay to violate the timing, of course. So I'll just assume this obvious answer is wrong for some reason.
I'll assume the question also doesn't mean something like "delay it by a half clock cycle", because who knows.
Now, f is a periodic signal, so to phase shift it by 180° a single inverter should be enough (neglecting delay). That's not in the answer list, so the question is probably about flops instead.
f's frequency is half the clock frequency, so delaying it by 180° means delay it by 1 clock cycle. And the output signal edges should be aligned with the clock negative edges. This means the second flop should have an inverter in its clock input, so it switches on negative clock edges. So we eliminate answer "b".
Answer "d" both inverts and delays f by 1 clock cycle, which is not what we want.
So it's either a or c which are identical. In this case the first flop latches in f when clock is riging, and the second flop latches it when clock is falling, resulting in a delay of 1 clock cycle.