How is high impedance state physically different from a logic low state?

Question

I have read this question and the answers that follow on the electrical stack exchange but I still face a difficulty in understanding the practical difference between high-Z state and 0 state. It is commonly used in hardware description languages. I know that the high-Z state is when the connection is removed. But I want to understand the physical difference.

My question is best understood with the help of this thought experiment:

Consider only the output terminal of a tri-state buffer is visible and available to me, and a demon (like the one in Maxwell's thought experiment) is applying 0 or 1 to the 2 inputs of the tri-state buffer. I have to detect when the terminal is tri-stated. I have only an LED and a NOT gate with me and both are of the same logic family as the tri-state buffer. I can ground my circuit.

First, I connect the LED to the output terminal of the buffer. I know that the LED will remain off when the output of the buffer is 0 and when the output of the buffer is tri-stated.

So instead, I'll place a NOT gate between the output of the tri-state buffer and the LED. So will the LED will be off only when a logic 1 is on the output of the tri-state buffer?

If so, is it possible to identify whether a terminal is tri-stated or 0 without measuring the resistance of the terminal?

Answer 1

Here's a possible implementation of a tri-state output.

If only the top FET is ON then the output is logic level 1.

If only the bottom FET is ON then the output is logic level 0.

If both FETs are OFF then the output is high-impedance, which means this particular output pin doesn't do anything to the actual voltage on the wire. If it is not driven to a valid logic level by some other component, like a pull resistor or another non-tristated output wired in parallel, then it has no defined logic level. Usually it is noted as logic level "X" which means "undefined". Actual voltage will be "whatever" depending on circuit parasitics like leakage or remaining charge in chip capacitance, and if this is fed to the input of another chip it may be interpreted as any random level, or cause excessive current draw if voltage is close to midsupply and both input FETs conduct.

If so, is it possible to identify whether a terminal is tri-stated or 0 without measuring the resistance of the terminal?

No.

You can use LEDs as you say in the question, here are examples:

On the left, if the gate outputs 1 or 0, only one LED will light up. If it is High-Z then both LEDs will light up if supply voltage is enough for 2 series LEDs, or no LEDs will light up if supply voltage is too low.

On the right, if the gate outputs 0 the LED will not light, if it outputs 1 it will glow strongly, and if it is High-Z the LED is connected to the supply via a high value resistor so it will glow weakly.

Answer 2

Your thought experiment needs more definition of where the LED is connected, what a 'not' gate is, and what 'measuring' means.

If the LED goes to GND, it will be off for tristate, and off for a driven '0'.
If the LED goes to VCC, it will be off for tristate, and on for a driven '0'.

If the NOT gate sources any current to its input pin (as does a TTL NOT gate, or an ECL NOT gate, whereas a CMOS NOT gate is pretty much open circuit), then when driven with a tristate pin, the output will go to a solid and reliable output level, depending on the direction of input bias current. With a CMOS gate, tristate input will mean the output of a NOT gate will not be predictable, but it will tend to keep the last state, due to the input capacitance maintaining the input voltage, in the absence of any discharge paths to GND or VCC.

What's a measurement of input resistance? ICs often use a 'weak pullup' or a 'weak pulldown', or even a 'weak pull to the middle' to determine whether the pin is connected to anything. If it's at the voltage that it's being 'weakly pulled to', then the decision is that the pin is not being driven, or is being driven by a high impedance three-state.

Answer 3

High-Z is an invalid logic level. It represents no connection to the circuit. It's the same as if the chip wasn't there at all.

If you measure the voltage, you might get somewhere between a 0 and a 1 depending on stray capacitance, leakage currents, and so on. Some types of logic gates will leak a small amount of current out of their inputs which will make the line 1. Some types consume a small amount on their inputs which will make the line 0. Some types consume no current and the voltage will change if you put your hand near it. (I'm not kidding, this really happens)

It is possible to detect a disconnected signal. Multimeters can measure resistance, and so can you. You could connect the line to high through a resistor, and see if it goes high, and then to low through a resistor, and see if it goes low. Or you could connect it to a different voltage (like halfway between high and low) through a resistor and see if it goes to that voltage. You don't want to feed the halfway voltage to inputs of logic gates though; they won't handle it correctly. It will take more circuitry than just using two separate binary signals to transfer 3 states.

The main reason that Hi-Z is used is when you want to connect a different output to the same wire. Like in a microcontroller - if you set a pin to input mode, the output part of the pin circuit goes to Hi-Z. Otherwise you could only input what it was outputting and you couldn't connect it to another output. This can also be used in some circuits to save power. They are also used in busses to ensure that only one device tries to talk on the bus at a time.

Answer 4

Think about an on off switch. In one position it connects the output wire to ground. This is equivalent of the output driver driving the output to low, so this is a low impedance state. In the other position, it disconnects it from ground. This is equivalent of the output driver driving neither low or high, so the output is not connected anywhere. That is the high impedance state.