I am interested in designing (with verilog) some memory structures that have multiple (let's say 3) read/write ports. I've been doing some studying on architecture and what I've heard is that these are not trivial hardware implementations, and can create a lot slower circuits.
With behavioural verilog I would imagine it's quite simple, something along the lines of:
always @ (posedge clk) begin if (read_enable) begin out1 <= mem[read_addr1]; out2 <= mem[read_addr2]; out3 <= mem[read_addr3]; end //something similar if I want multiple writes end
Assuming it synthesizes, will I have a crappy and slow circuit, and why? Can it be alleviated by going with a more custom design using gates instead of behavioural coding?