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Are there any implications if you have a design module as shown below where you have a duplicate case statement (duplicate case 2'b01 :)? As far as I known the execution is via precedence, so the second duplicate statement doesn't get executed. In terms of fabrication and any other reasons why this may not be ideal or it doesn't matter.

module jk_ff (input j, input k, input clk, output logic q); 
 always @(posedge clk) 
 case ({j,k}) 
 2'b10 : q <= 1; 
 2'b11 : q <= ~q; 
 2'b01 : q <= 0; 
 2'b01 : q <= ~q; 
 default : q <= q; 
 endcase 
 endmodule

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The implications will show up when you get to a real project.

It will show up when you get into code coverage. It's one of many ways you can create unreachable statements. SystemVerilog has a unique case that flags multiple matching case items during simulation.

BTW, It's also a bad idea to have q <= q; statements—leave that behavior implicit. It gets in the way of debugging or what called backdoor access. You try to set a register when you don't think it's being used, and your setting gets overwritten with the previous value.

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A good simulator should give you an error message, but I wouldn't bet my career on that.

A synthesis tool will certainly choke on this, because the different cases must be mutually exclusive. The logic you describe is not synthesizable.

Since you are intentionally inferring sequential logic there is no need for the default case...the flip flop will just keep its current value.

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In QuartusII this will be synthesized by the following:

enter image description here

so the first case 2'b01 : q <= 0; will only be considered.

However, it will signal the following warning (case item expression covers a value already covered by a previous case item):

Warning (10272): Verilog HDL Case Statement warning at question509393.v(7): case item expression covers a value already covered by a previous case item
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  • \$\begingroup\$ I'm disappointed in Quartus...that should be a hard error rather than a warning. \$\endgroup\$ Jul 13 '20 at 23:36

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