I'm studying about PLAs and I came across this simple PLA design.
What is the purpose of the highlighted transistors?
\$\begingroup\$
\$\endgroup\$
1
-
\$\begingroup\$ For reference, a transistor connected this way is often called a "diode-connected transistor". It's a more obvious where the name comes from if you're looking at BJTs instead of MOSFETs. \$\endgroup\$– Adam HaunCommented Jul 8, 2020 at 18:57
Add a comment
|
2 Answers
\$\begingroup\$
\$\endgroup\$
5
Those are depletion-mode1 NMOS transistors. They function as pull-ups or "loads" (effectively resistors) for the wired-NOR NMOS logic. When the source+gate connection is pulled low, they basically become current sources.
The key point is that pull-down (enhancement mode) transistors are placed at the cross-points in both the AND-plane on the left and the OR-plane on the right in order to implement the desired logic functions. The result is a direct implementation of a sum-of-products form of logic.
simulate this circuit – Schematic created using CircuitLab
1 As indicated by the fat "channel" line; an old shorthand notation. The other transistors in the diagram are the more familiar enhancement-mode devices.
answered Jul 8, 2020 at 12:56
-
\$\begingroup\$ Isn't that the digital symbol for a NMOS Transistor ?<br> and we must complete the diagram, perhaps that's why it's missing the inverting buffers. And can you explain a bit more.<br> Thank you <3 \$\endgroup\$ Commented Jul 8, 2020 at 13:03
-
\$\begingroup\$ No, the transistors at the bottom of the diagram without the fat "channel" line are the NMOS transistors. It's an old shorthand notation. Also, IIRC, there's something special about the doping of the PMOS "load" transistors. \$\endgroup\$ Commented Jul 8, 2020 at 13:07
-
\$\begingroup\$ Wouldn't the bulk connections be connected to VSS, and not to their sources as shown in your schematic? \$\endgroup\$– BrtHCommented Jul 9, 2020 at 0:07
-
1\$\begingroup\$ @BrtH: Yes, that's a limitation of CircuitLab, which does not have a symbol with the substrate brought out separately. They also do not have a proper symbol for a depletion-mode device -- I had to fake it by drawing an extra line over the enhancement-mode symbol. \$\endgroup\$ Commented Jul 9, 2020 at 0:10
-
\$\begingroup\$ @DaveTweed Thanks for the confirmation, just wanted to check. \$\endgroup\$– BrtHCommented Jul 9, 2020 at 0:14
\$\begingroup\$
\$\endgroup\$
To add to previous answer, reason is to use MOSFET as resistors caused that on IC level resistors are really space costly compared to good old MOSFET.
Compare size of 90nm PMOS and 500 ohm poly resistor on the picture. (90 nm ST CMOS tech)
