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I am simulating in LTSpice a switched-mode power supply (LT3845) at a frequency of 150kHz. I am measuring the loop gain at the feedback node according to this article.

The way I understand it, the simulated loop gain is only meaningful up to around ~1/10 of the converter switching frequency. Any frequencies higher than that and the converter can't react fast enough and the waveforms stop behaving in the linear region (cosine in, cosine out). Intuitively this says to me that the converter should be inherently stable from this point onwards to higher frequencies because it shouldn't be possible to be driven to instability when the converter itself cannot react to the speed of the disturbance (and instead settles for the average).

But then I look to a number of papers/articles that appear to measure real hardware loop gains using network analyzers into the MHz range. Why? I would expect the data to be meaningless above a certain point.

Edit: I did find one paper here that suggest I am approximately correct, see pg. 33.

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  • \$\begingroup\$ You can look at an answer I gave here. In high-speed dc-dc converters for graphic processor units or motherboards, designers now approach half of the switching frequency which is the upper theoretical limit. The reference often given as 1/10th of \$F_{sw}\$ is meaningless as crossover depends on the topology and the performance you want. \$\endgroup\$ Jul 8 '20 at 21:21
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The unity gain BW must have good phase margin at all load ranges and also good harmonic ripple attenuation which are design tradeoffs that increase complexity of the component selection.

e.g. Dissipation Factor or low ESR, Q or low DCR in the choke and FET RdsOn. The load current range affects the loop gain margin due to the impedance ratios, component values, lead-lag loop compensation filter and series-resonant frequency (SRF) of big reactors. (LC).

Although the curves are often benign well above the unity gain frequency, they are captured to ensure no spurious behaviours. That is defined by the yellow bar on your Figure B2 on p33.

Also some switchers operate in the low MHz to reduce reactor sizes but can make it more layout critical.

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  • \$\begingroup\$ I think that makes sense but I'm not sure it entirely answers my question. Is it to be understood that there is only one unity gain frequency? And if the unity gain frequency is approx. 1/10 of the switching frequency, how much further above the unity gain frequency would you go when measuring the loop gain to ensure there are no spurious behaviors? \$\endgroup\$
    – aosborne
    Jul 8 '20 at 18:22
  • \$\begingroup\$ Up to the switch rate typically, more if you are working on ripple reduction. \$\endgroup\$ Jul 8 '20 at 18:32
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The way I understand it, the simulated loop gain is only meaningful up to around ~1/10 of the converter switching frequency.

Not true in many cases.

I think you may not have grasped the enormity of the problem of the energy storage inductor and the output capacitor. These might be resonant around one-tenth of the switching frequency (that's not disputed) but they are within the feedback control loop of the switching regulator so, any additional phase change they bring about has to be under stood. So, lets use the example of a synchronous buck regulator operating at 500 kHz with 3 uH inductance and 3 uF output capacitance.

It will form a tuned circuit at 53 kHz and, with a light load (say 1000 ohms) will not produce any appreciable phase shift up to 52 kHz. Thereafter it will shift the phase of the signal from 0 degrees to -180 degrees between 52 kHz and 54 kHz.

This is what causes the main problem with switching regulators because that sudden phase shift produces an inversion and what was previously stable is now borderline unstable: -

This happens way down lower than the switching frequency and is the main reason why compensation is used. Here's the response when the load is 10 ohms. I'm showing it because it's easier to pick out the graphs: -

enter image description here

You can use this on-line calculator to try it for your self and note; that the higher the Q factor the greater is the sudden change in phase shift.

But, there can also be many cases where the resonance of the inductor and output capacitor is much closer to the switching frequency. The above was at one-tenth but it could all happen at one-third.

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  • \$\begingroup\$ I think I do understand the criticality of understanding where the resonating frequency is positioned and why a compensating feedback network is necessary to provide the converter with good gain/phase margin. What I'm trying to poke at is if your converter is operating at 500kHz switching frequency, up to what frequency is your loop gain measurement actually meaningful? When using a real switching converter, at some point the non-linear time domain characteristics should dominate and the entire concept of a linear system loop gain shouldn't be valid. At least that's my conjecture. \$\endgroup\$
    – aosborne
    Jul 8 '20 at 18:47
  • \$\begingroup\$ Aha you have an answer already. No need to explain eh? \$\endgroup\$
    – Andy aka
    Jul 8 '20 at 19:26
  • \$\begingroup\$ Well, I had accepted that answer prior to your initial response. Of course if you have more to add I would certainly be receptive to it. \$\endgroup\$
    – aosborne
    Jul 8 '20 at 19:46
  • \$\begingroup\$ I believe that it would be correct to raise this with the person who’s answer is accepted. \$\endgroup\$
    – Andy aka
    Jul 8 '20 at 22:17

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