IC datasheet and MOSFET selection question

Question

I am trying to design a buck converter using TI's LM3150 synchronous buck controller and I am wondering how to read some of these specs and how to select MOSFETs based on gate charge:

https://www.ti.com/lit/ds/symlink/lm3150.pdf?ts=1594337765626&ref_url=https%253A%252F%252Fwww.google.com%252F

It says VCC current limit is 65 mA, but why is the current limit is at VCC=0?

Thereotical you should size the MOSFET gate charge and switching frequency so that VCC current limit < (Qc_Total * FSW). However, in the past few days, I saw a couple of TI reference designs (for other power controller ICs) that didn't apply this rule and they paralleled a lot of FETS in each switch. In theory, it wouldn't work if the minimum current limit is really 65 mA (maybe this only happens at the extreme temperatures). Am I not understanding this right? Or maybe their designs are really only "reference" designs and not meant for production?

Thanks.

Answer 1

Here's the block diagram of the LM3150 internals.

So, VCC is normally regulated to ~6V by an LDO. This provides power to the drivers that do the actual switching. Because the role of the drivers is effectively to charge capacitors (the MOSFET gates), the important question is how much current the LDO can source on a consistent basis. C_VCC and C_BST handle the bulk of the short-term current demand; each is on the order of ~1uF, whereas a MOSFET gate might have a capacitance of ~10nF.

To test the LDO current sourcing, they short the VCC pin to ground (hence, 'VCC = 0V') and measure how much current can be produced by the chip. Reading from the table, 100mA is typical, and they specify at least 65mA will be produced over the operating temperature range. The relevant footnote says '(1) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.', i.e. you can't draw substantial current from the VCC pin for other purposes or the device is liable to overheat and shut down.

As to the second part of your question, you can parallel MOSFETs with relative ease, but the equation FSW * Q_total <= I_VCCL must still hold. Below is the example they included in the LM3150 datasheet.

In their example, Q_total comes out to 22nF, and the allowable upper limit is 130nF. If they wanted, they could double up each MOSFET, bringing Q_total to 2*22nF = 44nF, which is still significantly under the limit.

Lastly, the TI reference designs are there as examples that the chip does what they say it does, as well as to provide a implementation example with middle-of-the-road values. These sorts of designs aren't meant for direct production in the sense that the actual inputs/outputs/etc. for your particular application will likely differ in some way from the values they used, but these designs are meant to work as provided (they actually sell quite a few of their reference circuits as pre-fabbed boards). The LM3150 datasheet includes such a design starting on page 14 (the 'Application and Implementation' section). It goes through the design process in the recommended order and gives the equations to determine values for each part.