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I am designing a JTAG Controller using verilog. Now my question is :

As per the state diagram of JTAG IEEE standard, in the below diagram enter image description here

The Instruction /Data is loaded from a parallel register in Capture IR/DR state. The it can either go to shift IR/DR state or directly go to exit 1 IR/DR state if it need not shift. Finally, the FSM has to reach update IR/DR state after which a new instruction/data will be sampled. Till this point I understand, for which I have thought of a design as shown

enter image description here

As per my understanding, when the path selected in FSM is Capture IR-->Exit 1 IR-->Update IR, then the Load IR register will load data onto IR register when Capture_sel (from TAP Controller) is high.And IR will update to Update IR register when Update_sel is high. Other option being, after Capture IR state, next is Shift IR state, such that data loaded into IR register from Load IR is shifted serially into the Shift IR register every cycle of TCK. Finally both the paths reach update IR state, hence the IR value will be loaded into the Update IR from either IR register or Shift IR register depending upon which path taken from Capture IR state. Finally, data will be shifted out of Update IR state into TDO.

I want to know if my understanding is correct.

I also read that the TDO is driven Z (high impedance) when the state in not Shift IR/Shift DR which should mean that data is shifted out at Shift IR state and not wait for Update IR state to shift out. Which of these interpretations is correct?

If data is shifted out at Shift state, what is the need of Update state? Also, when the path taken is Capture IR-->Exit 1 IR-->Update IR, then it bypasses Shift IR state. Does that mean IR is not shifted out? What is the intention of doing so?

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JTAG TAP controller selects one shift register at a time in a set of shift registers. There is one special shift registers which is the Instruction Register (IR). Then there are an arbitrary number of Data Register (DRs). Data register is selected depending on current value of IR.

Shifting is performed when state is either Shift-IR or Shift-DR. You probably noticed that for getting to Shift-*, you are actually required to go through Capture-* (before) and Update-* (after). Overall, JTAG is able to express any combination of Run (Run test/Idle), Capture-shift-update on IR (with an arbitrary count of shifted bits), Capture-shift-update on IR-selected DR (with an arbitrary count of shifted bits).

Currently-selected shift register is directly connected to TDI and TDO. For a N-bit shift register, if you shift for more than N bits, you should get back on TDO what you inputted on TDI N bits before. That's what makes JTAG TAP daisy chaining possible.

When in Capture state, shift register should be initialized from semantically-matching register. For instruction register, two LSBs must be captuted to "01" (IEEE-1149.1 requirement). Other bits are implementation-defined. For DR, whether the captured value has a meaning or not, and whether the value is constructed from an actual register value or something else is dependant on the instruction and its semantics.

Shifting phase may be performed in parts (going through exit1, pause, exit2, and back to shift). This makes no difference. The only time where shift regsiter should be committed back is on Update state.

Now for the implementation, either you use:

  • only one shift register with a selectable length (through bypass muxes), fed from TDI, output connected to TDO;
  • multiple shift registers with enables (shifting is only performed when said register is selected), and a mux at the end to select which one drives TDO;
  • a mix of the two previous options (some shift registers shared, some not).

This is an implementation tradeoff, as you need either muxes for Capture (when constructing initialization value of shift register from other registers) or on TDO (for selecting driving shift register).

Actual architecture for you case depends on your TAP's complexity and its instructions.

JTAG TAP block diagram from Wikipedia perfectly illustrates shift register selection:

JTAG TAP (From Wikipedia)

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  • \$\begingroup\$ Thanks. I still did not understand what is meant by "committed back is on Update state". If shifting is the main intention, and maybe pause etc, then what is the use of Update state? What does it do? Why is there is a combination of Capture-exit1-update where there is no shift ? Also, does the Instruction decodes the instruction before it reaches Update IR state? \$\endgroup\$
    – shaam
    Jul 12 '20 at 14:43
  • \$\begingroup\$ Also, you said to load 01 in LSB during Capture IR state. But what if we want to pre-load an instructon like BYPASS where all 6 bits are 1 i.e 111 111 ? Then should I use other states e.g 6 states in Run Test idlde to allow TDI to preload th 6 bit instruction or do I use shift in TDI to spend 12 cycles in Shift IR ? \$\endgroup\$
    – shaam
    Jul 12 '20 at 14:46
  • \$\begingroup\$ Update state is when shift register is copied back to actual instruction/data register. If you assert TRST, you get back to Test Logic Reset without changing register value, for instance. IR is decoded from IR register, not from shift register. It should be decoded after Update only. \$\endgroup\$
    – Nipo
    Jul 12 '20 at 17:11
  • \$\begingroup\$ IEEE-1149.1 mandates you preload IDCODE or BYPASS in IR on reset, but then, the only way to change IR is to go through Capture-shift-update-IR sequence. There is no provision to read back current IR, IR shift register is not initialized with current IR, but with TAP-defined bits, and fixed LSB (per spec). For instance, look at spartan-6 IR capture value in UG380, Table 10-3 \$\endgroup\$
    – Nipo
    Jul 12 '20 at 17:18
  • \$\begingroup\$ To be more specific, Update state is where you say "I'm done shifting". Before reaching Update, ATE (the equipment driving JTAG pins, per spec terminology) may still go back to shift and change the register contents. TAP should not interpret register value before it is certain ATE is done shifting, i.e. going through Update. \$\endgroup\$
    – Nipo
    Jul 12 '20 at 17:27

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