I'm building a frequency synthesized local oscillator with coarse and fine tuning to span 30.5 to 32MHz. The design follows the following block diagram (bits not essential to this question removed for clarity):

enter image description here

Coarse tuning is done through the ADF4002 phase locked loop (PLL) IC in 5KHz steps. For fine tuning, I'm using an AD9851 DDS module. The DDS signal is mixed (NE612) with the VFO to produce a 25MHz IF, which is filtered through a BPF (3rd order Cheby) centered on 25.25MHz. The PLL will divide the 25MHz signal and lock to the 5KHz reference signal (derived from a 20MHz crystal by the PLL.)

I elected to use the Analog Devices ADISim tool to choose the component values for the LPF and I opted for a 4-pole active design where the target frequency was 30.5 to 32MHz. I chose the fast settling time option and the tool returned the following circuit:

enter image description here

enter image description here

Unfortunately, I'm having a problem where the PLL won't lock. I can get it to lock (but with an extremely jittery output) if I apply a voltage to the VCO input that puts the VCO somewhere in the 30.5MHz zone. When I remove this voltage, the PLL will remain locked providing it's coarse setting is tuned to the upper part of its range. If I lower the range setting, it unlocks (and the jitter stops.)

Now here's the thing, in a previous incarnation of this circuit I had the coarse tuning part working driving a VFO from 34.5 to 36MHz. I had used the exact same low pass filter design but with different component values (as dictated by ADISim for that particular target frequency range.) So, I know there's no issue with my PLL board. I've tested the 25MHz band pass filter independently and its bandwidth is wide enough to cover the frequencies of interest.

I think the issue is with the PLL LPF and here's my question:

Should I have asked ADISim to design the filter based on a target frequency of 24.5 - 26MHz rather than the VCO frequency of 30.5 to 32MHz?

In other words, where a mixer down-converts the VCO frequency in the loop, what loop frequency are you really working at?

If you need any more detail I'm happy to post it up. This is a complicated circuit, so I've left out bits that I suspect are working fine.

  • \$\begingroup\$ Stabilising a 4th order filter in a closed loop is ... not easy. Why choose a 4th order filter in the first place? What requirement are you trying to satisfy with it? (And it's at about 1 kHz not 30MHz anyway). From the control theory I remember, anything above 2nd order tends to instability. \$\endgroup\$
    – user16324
    Commented Jul 12, 2020 at 19:46
  • \$\begingroup\$ @Brian I must admit, this is all pretty new to me. The reason I chose this filter design is that I came across a similar project online using the same PLL IC. They used the same filter topology, as far as I could make out. The ADISim tool describes this filter as having "greatly increased rolloff better attenuation of noise and spurs" and I needed an opamp to drive the VCO. The thing is, it worked flawlessly at 34MHz with no down-conversion. \$\endgroup\$
    – Buck8pe
    Commented Jul 12, 2020 at 20:19
  • \$\begingroup\$ Also, I should have mentioned that I'm not sure if the high frequency output of the PLL has any influence on the LPF. What I do know is that when I changed my VCO frequency from 34.5-36MHz to 30.5-32MHz, the tool changed the component selection for the LPF. Seems that the VCO frequency selected does play a part? \$\endgroup\$
    – Buck8pe
    Commented Jul 12, 2020 at 20:25
  • \$\begingroup\$ It looks like a 3 pole filter to me. \$\endgroup\$
    – Andy aka
    Commented Jul 12, 2020 at 20:59
  • \$\begingroup\$ From 1M to 100M the attenuation increases by about 160dB, or 80dB/decade, which is a 4th order response. Andy's correct that the filter itself is 3rd order (slightly modified by a lead-lag network R2/C2/C3) - the additional pole comes from the VCO itself, as phase is the integral of frequency. It's likely the lead-lag network is an attempt to stabilise a loop with a 3rd order filter, and may need tuning according to the VCO frequency. Adapting it ... the VCO has gain (Hz/V) and so does the phase detector (volts/radian) and these are modified by frequency division. This affects stability. \$\endgroup\$
    – user16324
    Commented Jul 12, 2020 at 22:10

1 Answer 1


The PLL is working fine without the Mixer and LO? What is the bandwidth of the bandpass filter that you're using? Since the VCO and DDS tune over a couple of MHz, I suspect that anything that you're introducing with that will be invisible to a 1 kHz loop filter bandwidth. I'd propose two things to help debug this. First, use the simplest passive loop filter that you can, a simple 2nd order would work fine, as you've got no locktime/phase noise requirements. that will simplify the system. Second, look at the output of the DDS on a spectrum analyzer to see that the spurious level looks like-You could have some close in DDS spurious causing jitter.

  • \$\begingroup\$ I've changed the architecture slightly since I asked this question. I'm now (roughly) following the offset mixer scheme suggested by Morgantini in the July/Aug edition of Qex 1998 (see "A Continuous Coverage HF VFO"). My plan is to take an 8MHz crystal, triple that; mix it with 5MHz DDS - so 29MHz LO with fine tune. Then mix that with VFO operating at 23MHz (20M band + 9MHz IF). This is the offset mixer in the loop (so same idea). The diff freq (6MHz) is fed to PLL IC (whose min freq is 5MHz). \$\endgroup\$
    – Buck8pe
    Commented Feb 13, 2021 at 8:35
  • \$\begingroup\$ A relatively simple LPF after the offset mixer will produce the 6MHz signal. This avoids me having to use a BPF, with the accompanying issues you mentioned. I've got most of that built now, just the LPF and amps left. I'll update this question if I manage to get it going. \$\endgroup\$
    – Buck8pe
    Commented Feb 13, 2021 at 8:41
  • \$\begingroup\$ A 30 MHz continuous sweep in that range is fairly straightforward with an Si5351 part. You've got a fairly complicated architecture there. \$\endgroup\$
    – rfdave
    Commented Feb 13, 2021 at 19:32
  • \$\begingroup\$ That's true, but I'll know a hell of a lot more about PLLs when I'm done and that's more important than building a VCO (or even having something that works). \$\endgroup\$
    – Buck8pe
    Commented Feb 13, 2021 at 19:52

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