Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ODT feature, however Address, Command, Control and Clock do not have the same ODT selection. None of these lines have termination resistors either. It is a working reference design, however I am unsure as to how and why the lack of termination is permissible in this case. Differential clock doesn't even have parallel termination.
I was not able to find any online source to indicate whether it is ok to leave point to point design unterminated (not counting ODT which is available for data/strobe/mask). If anyone could please refer me to a link/document I would greatly appreciate your help.