Main signals comes under the source-synchronous group are data, ECC and strobe lines. My understanding about source-synchronous signal is that all of these signals would be latched on both edges of the clock signals and the direction of clock and source-synchronous signals are be same. What is source clocked signals? How is it different from source-synchronous signals? ( Source clocked signals - Address, Bank address, bank group, clock enable etc)
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Nothing. They're the same thing if you're talking about DDR3 or DDR4.
You're probably thinking that there's something to this based on Intel's use of the term, for example in this doc: https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-ddr2-ecc-so-dimm-paper.pdf
Don't be misled. In reality all the signals in DDR4 are source-synchronous. The ADDR/CMD group references CLK, and all are launched from the host together; while DQ references DQS which is launched from the host on writes and from the DRAM on reads.
In fact, multi-chip DDR3 and DDR4 explicitly rely on source-sync clocking to support daisy-chain (fly-by) routing. They have the added ability to level the ADDR/CMD/CLK to DQ delay which allows the DQ/DQS signals on a multi-chip rank to have less skew (that is, similar CMD to DQ latency.)
answered Jul 13, 2020 at 23:01