I am programming a Microsemi M2Gl005 FPGA and wondering which type of reset I should use. I currently have an asynchronous reset implemented, but I wanted to make sure that the part didn't prefer a synchronous reset. I checked the datasheets and found not much mention of it. Any thoughts?
The FPGA’s pin-level reset should not depend on any internal FPGA-resident clock, otherwise you can run into a ‘chicken and egg’ problem where your reset fails to propagate.
Instead, you treat that pin reset as asynchronous and use internal logic to create the kind of reset that you need.
It’s a good thing then that an FPGA can make a reset tailored to suit your application.
A couple of cases:
If your downstream logic requires a sync reset (as is often the case with systems using AXI or APB) you would run the (external, async) reset through a synchronizer block that’s clocked in that logic’s clock domain.
Further, if your logic uses a PLL to make the local clock, you also want the domain-specific reset to include the PLL’s lock status. Check your FPGA library, it will likely include such a block that does this.
If your logic needs to work in the absence of a reference clock you’ll use the async reset. But, you will need to deal with the clock domain cross if the output of such a block feeds synchronous logic, or specify the reset-exit as a false path.
For the latter reason it’s usually simpler to use an internally—synchronized reset as this avoids clock domain violations.
This choice will depend a great deal on the application and use cases of the FPGA. Does it get reset only when first powered up or is it reset periodically during operation? Is the reset generated internal to the FPGA or externally? Can you synchronize the reset input when it enters the FPGA and then use it as an asynchronous reset?
It is important that you consider metastability when making this decision. If you have a truly asynchronous input to a synchronous design then metastability can happen.