0
\$\begingroup\$

The Synopsys Synplify Pro is used internally to carry out synthesis in Libero and probably other places. Is there a method to assign a tcl or python script to be executed just before or just after synthesis?

A script that runs just before synthesis can be used to generated compile date and time into a VHDL file that will then be compiled into the project.

\$\endgroup\$
4
  • 1
    \$\begingroup\$ If you dig into how Synplify runs you will find such a script already exists. I have had to modify it on one installation that messed up the OS version number checks on a Linux box (and exited without running), but it would be possible to hook in other things too. \$\endgroup\$ – user_1818839 Jul 15 '20 at 23:45
  • 1
    \$\begingroup\$ See for example Libero_v11.8/Synplify/bin/syn_system_check (which is a shell script) \$\endgroup\$ – user_1818839 Jul 15 '20 at 23:53
  • \$\begingroup\$ I see, as long as it does not get overwritten automatically, it will be able to solve my problem \$\endgroup\$ – Quantum0xE7 Jul 16 '20 at 4:26
  • \$\begingroup\$ @Brian, this file does not exist, I did find a synhooks.tcl but it is not project specific. There are several tcl files inside the project directory that might be getting called when compilation starts, but, they are basically overwritten automatically each time. \$\endgroup\$ – Quantum0xE7 Jul 20 '20 at 0:03
0
\$\begingroup\$

In Libero SoC design flow options. Right-click and select the synthesize options. Now add path to the script under the additional options for SynplifyPro synthesis. When this script executes, it shall print into the synplify.log.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.