I have a parallel EEPROM, the AT29C020 (doc: http://pdf.datasheetcatalog.com/datasheet/atmel/DOC0291.PDF)

In order to read it I'm using an ATMega8535 as it has enough pins.

At first I thought reading the chip would be easy but after several attempts I have to admit I don't have a clue about what is going on here. If I correctly understand the spec, you put the address on the address lines, then you put CE and OE low to enable the chip and the reading process and finally after some time (far less than 1µs) the chip outputs the content on the data pins.

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I'm doing this and it doesn't work. More precisely, here is what I do:

  • everything as output (DDR* = 0xff)
  • everything high (PORT* = 0xff, thus including WE)
  • CE low
  • (*) data lines as input
  • put the address on the pins
  • OE low
  • 1µS sleep
  • read data pins
  • OE high
  • 1µS sleep
  • go to read next address => (*)

Instead of receving the data, I have the pattern that the doc describes as the I/O6 bit toggling, which is a method during the write operation to know if it has finished. This means every read returns the same value except for the 6th bit that toggles for each read. For example I saw 31/95 and 159/223 patterns. Also, it never ends and doesn't depend on the input adress.

TOGGLE BIT: In addition to DATA polling the AT29C020 provides another method for determining the end of
a program or erase cycle. During a program or erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a
program cycle.

Obviously I'm neither programming nor erasing so I really don't get why the chip reacts this way. I searched a lot before coming here but sadly I can't find anything. By the way I don't think it's hardware related because I tried to put a long pause while reading and the address/CE/OE/WE are correct.

  • \$\begingroup\$ You should set the port to 0xFF BEFORE setting the pins as outputs, otherwise you have a brief low on all of the signals before you set them high. You should also have a pullup resistor on the WRL and CEL lines to make sure that they high before the port is output enabled. \$\endgroup\$
    – crj11
    Jul 16, 2020 at 2:44
  • \$\begingroup\$ You are doing things in the wrong order, the address should be valid before CE goes low. I doubt the chip is synchronous with it, so it doesn't explain your problem but you are still "doing it wrong" to set CE before the address. How do you know what the contents should be??? \$\endgroup\$ Jul 16, 2020 at 2:50


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