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Is there any special reason because of which active-low inputs are occasionally used instead of active-high inputs? Example: We have active-low inputs RD' (read as "READ bar") and WR' (read as "WRITE bar") for memory chips, instead we can have RD and WR as inputs right?

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Almost fifty years ago, the dominant semiconductor technology was the (usually NPN) bipolar transistor, in the form of 74-series TTL logic.

This led to input stages that required some current to pull them low, and much less to pull them high - and conveniently, to output stages that were much better at pulling signals low, but could not pull signals high very effectively. (Study "The TTL Data Book" from Texas Instruments for more details)

And so, important signals like RD_n, EN_n, WR_n and RESET_n where the timings really mattered, worked better if you made them active low.

Every new design since then has remained compatible with this convention, so that they can be interconnected with existing devices, though with the advent of high speed CMOS logic, there is really no technological need.

So the reasons are compatibility (the way many CPUs have instruction sets still vaguely compatible with the 8086 from 1978) and engineers and worse, teachers, mainly familiar with the old convention.

A bit like the Space Shuttle booster size being linked to the width of a horse's butt in Roman times.

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    \$\begingroup\$ In addition, when the output was inactive when high, there was better noise immunity than in the active state which tended to be active with a low duty cycle. \$\endgroup\$ – Peter Smith Jul 16 '20 at 11:26
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    \$\begingroup\$ not only that pulling low needs much higher current than "pulling" high, but the TTL input topology actually works like in internal pull-up. So an active-low control signal is inactive when it is not driven at all, whereas an active-high control signal would be active when it is not driven at all. (Note that the "implicit pullup behavior" is true for 74-series and 74LS-series chips, but not necessarily for CMOS chips like 74HC or 74HCT). \$\endgroup\$ – Michael Karcher Jul 17 '20 at 1:01
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    \$\begingroup\$ @MichaelKarcher That's true, but It was unwise to regard an undriven input as guaranteed high in a moderately noisy environment; 4k7 or 10k pullups were normally used. \$\endgroup\$ – user_1818839 Jul 17 '20 at 9:26
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Brian's "legacy" answer is quite fine.
There is another reason why active low is somewhat more reliable than active high in modern CMOS designs, and why it shouldn't disappear soon.
This reason involves a huge variety of CMOS supply voltages. We often encounter systems where some modules have 3.3V supply, while others have +5V supply. These modules likely don't agree where a high voltage begins. But the maximum low voltage is likely more agreeable. Communication between these two systems has better noise immunity for a low-voltage logic level than for a high-voltage logic level.
Today's CMOS logic level thresholds are often defined at some fraction of DC supply voltage:

  • logic high: 0.7*Vdd
  • logic low: 0.3*Vdd

Many modules that communicate over a bus should prefer low-voltages over high voltages for critical signals.
For example, the I2C serial protocol idles at a high voltage level (pulled up passively by resistors). All critical signals pull actively to ground. One might argue that this design is classic old-school legacy-style, introduced in 1982 when old-school TTL technology was still in wide use.
BUT...
This "pull-to-ground" design using open-drain bus drivers allows the bus to be driven by many devices, in wire-or fashion. And it can allow bus receivers to tolerate a bus pull-up voltage higher than a microcontroller's own Vdd...look for 5V-tolerant I/O. Every bus-connected device agrees that ground is zero volts. Not every bus-connected device agrees on Vdd.
Pull-to-ground still has advantages in modern logic design.

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    \$\begingroup\$ You bring up many important points missed by Brian+1. Also old DTL logic used the same active low enables, so the value of Vdd was not important, even if it was 12 volts. Coupling different logic voltages often only needed a fast diode (1N4148) to pull a pin low enough to work. This will not work with todays super-fast PECL logic. \$\endgroup\$ – user105652 Jul 17 '20 at 1:56

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