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I bought some SOM modules with AM335x on board (PH8700). The SOM is completely blunk (both eMMC and EEPROM). So I have to build u-boot spl first and load it via XMODEM. The problem is that u-boot spl hangs between board_init_f() and board_init_r(), it seems that the bad thing happens while relocating the stack from SRAM to DRAM. Specificaly when I comment the following code in ctr0.S:

# ifdef CONFIG_SPL_BUILD
#   /* Use a DRAM stack for the rest of SPL, if requested */
    bl  spl_relocate_stack_gd
    cmp r0, #0
    movne   sp, r0
    movne   r9, r0
# endif

u-boot SPL goes further. Does it mean that I have some problems with DDDR3L? Do I have to retune it in u-boot? Why is that? The board doesn't seem to be changed, and the previous versions worked fine... P. S. I've tried different versions of u-boot (mainline, TI, some custom versions for PH8700 module, TI versions, etc.). The result is always the same - SPL freezes between board_init_f() and board_init_r(). How can I resolve that issue?

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  • \$\begingroup\$ Read what the code in those functions does, examine the board more carefully. Perhaps one of the memories changed. \$\endgroup\$
    – Chris Stratton
    Commented Jul 16, 2020 at 14:10
  • \$\begingroup\$ Yes, It seems that DDR3L chip have changed from MT41K256M16HA-125 to D2516EC4BXGGB... But they should be identical... Does it mean that I should calibrate u-boot settings for DDR over again? \$\endgroup\$
    – Andy
    Commented Jul 17, 2020 at 5:48
  • \$\begingroup\$ I tried to tune u-boot settings acording to AM335x EMIF toolv3, but nothing have changed, SPL stuck at spl_relocate_stack.... \$\endgroup\$
    – Andy
    Commented Jul 17, 2020 at 13:36

1 Answer 1

Reset to default
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I figured things out. The problem was in SRAM settings in u-boot. Now SPL and u-boot loads properly. Just in case here are my settings that i changed for Kingston DDR3L chip:

/* Kingston D2516EC4BXGGB on PH8700*/
#define D2516EC4BXGGB_EMIF_READ_LATENCY 0x07
#define D2516EC4BXGGB_EMIF_TIM1 0x0888A99B
#define D2516EC4BXGGB_EMIF_TIM2 0x285B7FDA
#define D2516EC4BXGGB_EMIF_TIM3 0x501F857F
#define D2516EC4BXGGB_EMIF_SDCFG 0x63815332
#define D2516EC4BXGGB_EMIF_SDREF 0x0000049e
#define D2516EC4BXGGB_ZQ_CFG 0x50074BE4
#define D2516EC4BXGGB_RATIO 0x80
#define D2516EC4BXGGB_INVERT_CLKOUT 0x0
#define D2516EC4BXGGB_RD_DQS 0x38
#define D2516EC4BXGGB_WR_DQS 0x44
#define D2516EC4BXGGB_PHY_WR_DATA 0x7D
#define D2516EC4BXGGB_PHY_FIFO_WE 0x94
#define D2516EC4BXGGB_IOCTRL_VALUE 0x0000018B
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