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Due to tight space constraints I need to pass my LTE signal (800-1800 MHz) through a via. The proximity between the antenna connector and the modem is very short (literally on the other side of the pad).

Using impedance calculators, I have found that via diameters/ pads need to be somewhat small (Hole = 12, Pad = 18, Ref plane opening = 32 mils). However impedance controlled signal traces on a 2 layer 63 mil thick PCB are generally pretty wide: 33 mil width with 4mil conductor gap.

My question is how am I to connect the trace to the via when the trace width is substantially larger than the via pad diameter. If I connect it, I would effectively be increasing the via pad diameter to the trace width (33mil), and mess up my impedance.

Thoughts?

Also, here is an image of my PCB with the modem on the top layer, and a u.FL on the bottom layer. Please let me know if you have better ideas on how to connect this or if you see something wrong.

Thanks.

enter image description here

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  • \$\begingroup\$ Do you need to use a 2-layer board? 4-layer boards are quite cheap these days (even for hobbyists, from both Oshpark and JLCPCB). \$\endgroup\$ Jul 17, 2020 at 2:26
  • \$\begingroup\$ @LosFrijoles in hind site maybe I should have used a 4 layer, but at this point its already very complicated with over 250 components set. Would there have been a benefit in this specific instance? \$\endgroup\$
    – Troy Cados
    Jul 17, 2020 at 2:32
  • \$\begingroup\$ Your PCB picture confuses me. Where is the controlled impedance trace on the other side of the via? Which colors are top metal and bottom metal? Is your controlled impedance line coplanar waveguide with ground, or what? I see a ring of vias around the device,but they connect to nothing? \$\endgroup\$ Jul 17, 2020 at 4:49
  • \$\begingroup\$ @MartinStiko The three orange pads are the pads of the modem itself, so there is no trace on the top layer. Then the via goes to the bottom layer where the uFL connector (4 blue pads) sits directly under the modem. The ring of vias is for isolation stitching. The only trace I have is on the bottom layer from the via to the signal pad of the uFL connector. Since the signal line is directly below itself on both sides of the board I guess its not really a coplanar waveguide. Again I'm not confident this is a proper solution, I'm trying to make it work within my space constrictions \$\endgroup\$
    – Troy Cados
    Jul 17, 2020 at 6:57
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    \$\begingroup\$ A 4 layer PCB would allow you to reduce the size of your controlled-impedance traces on the surface of the board and also likely allow you to increase the size of your vias so that it is easier to design. \$\endgroup\$ Jul 17, 2020 at 14:21

3 Answers 3

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Conceptually, the starting point is the signal via and a ring of ground vias around it, treated as a short coax cable so that you can use the coax cable formula. The ring of ground vias cannot be smaller than the ground pads (since they must terminate there). The datasheet says edge-to-edge of the uFL groundpads is 1.9mm, so I imagine a ring of ground vias with a 3mm diameter. Are you using FR4 with a dielectric constant 4.4? This coax impedance calculator says 50 ohms for a Dk of 4.4, the OD of the signal via = 0.4mm and the ID of the ring of ground vias = 2.2mm.

The ring of ground vias does not have to be a circle, of course. You can use ATLC to calculate the impedance of an arbitrarily-shaped pattern of signal via(s) and ground vias. You just draw the signal region (red), ground regions (green) and dielectric regions (other colors) in 24-bit BMP. ATLC assumes that this set of regions forms a long transmission line, and calculates the impedance.

You then have to design the pads (with thermal relief) that the vias will land on, in the bottom and top metal layers. In theory, you could use ATLC for those also, except that the "long transmission line" assumption is very broken now. Also, what do you use for the Dk in ATLC, if you are at an FR4/air interface? I don't know - Dk = average(FR4, Air)? If you have confidence that the footprints for the uFL receptacle and the modem are designed for 50 ohms for your substrate, you can put them into ATLC and see which Dk gives 50 ohms. (Dk should at least be between FR4 and air, probably closer to FR4).

All of the groundplane outside the inner edges of your ground pads is irrelevant to the characteristic impedance, so you can put thermal reliefs there at will.

At 1.8GHz, 63mil is a very short transmission line, so your real questions are about lumped element capacitance and inductance. You can use FastCAP to calculate the capacitance between the signal and grounds, and FastHenry to calculate the round-trip inductance(?) . Then just move things around until sqrt(L/C) = 50 ohms.

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  • \$\begingroup\$ Thanks Martin, That was some great information. I had a fun time learning ATLC and it really is a nifty tool. \$\endgroup\$
    – Troy Cados
    Jul 21, 2020 at 6:04
  • \$\begingroup\$ There is a newer version, but for some reason it has never worked for me. \$\endgroup\$ Jul 24, 2020 at 3:51
  • \$\begingroup\$ @Troy Cados: Incidentally, I have a nice workflow for ATLC: 1) section my PCB RF trace, 2) take a photo through my microscope, 3) Using photoshop lasso tool, trace out the signal, ground and dielectric regions 4) fill in with correct colors, 5) calculate with ATLC. Since impedance does not care about the absolute scale, it is very easy to calculate the correct impedance. If the impedance is wrong, adjust whatever dimension is easiest to change in fabrication, and tweak until ATLC gives the desired impedance. Then built it. \$\endgroup\$ Jul 24, 2020 at 3:58
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Another aspect to keep in mind is the return current via. The path the return current takes also influences the impedance of the interconnect. It looks like the red stitching vias around this section will connect ground planes on the top and bottom layers. The return current for this signal will likely go through the nearest stitching via.

Instead of counting on that return current, you might like to engineer the return current by providing a return via (or multiple) next to the signal via. The size and spacing between the signal and return vias will impact the impedance of the interconect. (see page 12)

My 2c on connecting your large trace to the smaller via is it probably won't matter. I think there would be more cause for impedance discontinuities due to the large size of the pad itself, and the via / return via construction.

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  • \$\begingroup\$ I can't really help the size of the pad, but I can populate some return Vias. Do you think its okay to place these return Vias directly on the ground pads of the modem as well? \$\endgroup\$
    – Troy Cados
    Jul 17, 2020 at 7:01
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Your remaining degree_of_freedom is the separation between Trace and the Surrounding Ground fills.

And remember you can use TWO vias, or more.

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Use your 2_D or 3_D EM solver to explore this.

I've read (on stackX) that Vias can be thought of a 1nanoHenry inductance.

A couple of vias may (ideally) be 1nH/2 = 500 picoHenry.

Just giving you ideas.

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  • \$\begingroup\$ Is it a problem the way I have laid it out? I don't understand how using two Vias would help, or how to appropriately lay out two Vias in a beneficial way. Could you please expand on this? Thank you. \$\endgroup\$
    – Troy Cados
    Jul 17, 2020 at 3:13

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