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I have a general question regarding the placing of decoupling capacitors.

Example at DC Vout of SMPS or LDO regulators. Does it really matter which capacitor out of 100nF, 1nF and 10uF is placed closest to the Vout?

Also, when both electrolytic and ceramic capacitor are used where should they be placed?

What order would be best in terms of noise/ripple considerations?

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The smaller cap closest to output should help with radiated noise. Larger caps deal with lower frequencies (and tend have more self-inductance) so can tolerate more trace inductance so can be farther away.

Electrolytic vs ceramic capacitor is moot in the face of what I just outlined since type implies capacitance and self-inductance. Your electrolytics are always larger and slower than your ceramics.

It follows all the same principles of capacitors on inputs to ICs.

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