Is my understanding that, for a given technology, the cost of making a silicon wafer is pretty much fixed, in the sense that it will not change no matter how much you fill the space (how many ICs you can squeeze in a single wafer.)
Once the wafer is finished, it will come the time to dice the wafer to separate all the ICs. My understanding here is that a saw comes in and cuts between the dies separating them.
This saw will have a finite thickness, even though I wasn't able to find a figure on the internet. For the sake of the argument let's say that a reasonable thickness is 0.5mm. There are some very small ICs out there. Once again, I wasn't able to find a precise figure, but let's say that my IC is 1x1mm.
Let's now take a look at one cell.
It appears that, for every square millimeter of useful product, we are wasting 1.25 square millimeters by sawing them off, getting a yeld even smaller than 50%.
This won't be an issue for big dies as the percentual drop in yield would be far less, but how did the industry got arround this problem for small die ICs? Sorry if the numbers aren't accurate, this is just an example, I don't know how realistic it is.