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Is my understanding that, for a given technology, the cost of making a silicon wafer is pretty much fixed, in the sense that it will not change no matter how much you fill the space (how many ICs you can squeeze in a single wafer.)

Once the wafer is finished, it will come the time to dice the wafer to separate all the ICs. My understanding here is that a saw comes in and cuts between the dies separating them.

enter image description here

This saw will have a finite thickness, even though I wasn't able to find a figure on the internet. For the sake of the argument let's say that a reasonable thickness is 0.5mm. There are some very small ICs out there. Once again, I wasn't able to find a precise figure, but let's say that my IC is 1x1mm.

Let's now take a look at one cell.

dicing

It appears that, for every square millimeter of useful product, we are wasting 1.25 square millimeters by sawing them off, getting a yeld even smaller than 50%.

This won't be an issue for big dies as the percentual drop in yield would be far less, but how did the industry got arround this problem for small die ICs? Sorry if the numbers aren't accurate, this is just an example, I don't know how realistic it is.

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    \$\begingroup\$ In short, you're asking how smaller dice are economical as the die area decreases while the relative area lost due to saw kerf increases. I don't know the answer but price per chip would still fall since you are still getting more chips out of the same wafer, but it would start to taper off rather continue to fall linearly since you lose more and more to saw kerf but are still getting more chips per wafer. \$\endgroup\$
    – DKNguyen
    Jul 17, 2020 at 14:58
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    \$\begingroup\$ The saw street widths are usually less than 0.5mm, closer to 0.05mm. \$\endgroup\$
    – Justin
    Jul 17, 2020 at 15:19
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    \$\begingroup\$ Here's a paper about it: ieee-epsmalaysia.org/iemt/wp-content/uploads/2018/08/SUB603.pdf \$\endgroup\$
    – Justin
    Jul 17, 2020 at 15:23
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    \$\begingroup\$ It isn't a "problem" -- you still make a profit on the wafer. In other words, it's still better than not making the wafer at all. You just price the dice accordingly. \$\endgroup\$
    – Dave Tweed
    Jul 17, 2020 at 15:24
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    \$\begingroup\$ In addition to everything else that's been said, some of that space can also be utilized for etest structures. \$\endgroup\$
    – Annie
    Jul 17, 2020 at 20:16

2 Answers 2

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In general: Yes. You're losing area through the dicing street as the way the saw runs through is called.

However, your assumption of the thickness is wrong. The saw is more like a thin foil. Usually around 20 micrometers thick (factor 25 thinner than you assumed) and I've seen very specialized ones that were even thinner around < 8 micrometers. As a comparision: Typical bond wire pads (where the wires are connected to the Chip) are around 30-50 micrometers big. So your saw is thinner than the outer pad ring of the chip.

If you have a dicing saw in your hand it's kind of wobbely and does not very much look like a "saw". It is only able to cut the wafer because it is spinning at very very high speeds, which stabilizes the blade. The saws also have a very limited lifetime becuase of their small thickness. Usually they can only cut a few thousand meters before they need replacement.

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    \$\begingroup\$ Woah, those things must have some pretty cool engineering inside of them. \$\endgroup\$
    – Dan
    Jul 17, 2020 at 23:04
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    \$\begingroup\$ This is just something I quickly pulled out: disco.co.jp/eg/products/catalog/pdf/zh05.pdf Look at the last page. There is a parameter called kerf width. In this saw series it can go down to 17.5 um \$\endgroup\$
    – GNA
    Jul 18, 2020 at 8:08
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    \$\begingroup\$ I suspect that the kerf width/blade thickness is somewhat smaller than the 'street' that the blade cuts along - there is a section of dead space left on either side to account for tracking issues and possible damage. \$\endgroup\$ Jul 18, 2020 at 8:12
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    \$\begingroup\$ Yes. I remebember for one ASIC I did, that the design rules specified, that each ASIC must have a 25 um tick dicing area around it. Which makes a total of 50 um between two asics. However, I do not know what kind of a saw was used in that particular case. Probably around 30 um or so. Dicing saws are very precisely made. Also the height of the saw blade is very critical. The wafer is glued to a blue tape and then diced. The wafer saw has to cut through the entire wafer but must not cut through the foil on the back or everything would fall apart. \$\endgroup\$
    – GNA
    Jul 18, 2020 at 8:25
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    \$\begingroup\$ Silicon is a very cheap material. It's one of the most common elements found on our planet. The price of a wafer is dominated by the complex process of growing a monocrystaline block of silicon and purifying the silicon. As far as I know, the saw dust is just thrown out as garbage (unless there are dangerous substances on the wafer) \$\endgroup\$
    – GNA
    Jul 19, 2020 at 17:28
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There is also Stealth laser dicing, which has "zero kerf". The laser creates a tiny stress fracture inside the silicon, and the laser focal point is passed along the dicing channel multiple times at different heights within the silicon. Then the wafer is stretched, and the stress-fractured planes break. No silicon material is lost.

The kerf is not actually zero - the dicing street must be as wide as the accuracy of the laser positioning system, which is about +/- 5um (so the street is 10um wide).

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