Ethernet 1Gbps - PCB stackup

I am planning a stackup for 2x Ethernet phys. The chip requires a few different supply voltage levels: I/O Power 3V3 (3 pins) and Analog Supplies: VDD2V5 (2 pins) and VDD1V0 (4 pins). Each pin has both 100nF and 1uF caps. I don't have other signals on the board. The board will have 24V/3V3 iso DC/DC convereter and two LDOs 3V3/2V5 and 3V3/1V0. The board is not excessively complicated however I am thinking of a 6-layer stackup because of those different voltages. The phy IC will bo on top layer, power DC/DC and LDOs on the bottom. The layers:

• TopLayer: Ethernet signals
• Mid1Layer: GND
• Mid2Layer: 2V5
• Mid3Layer: 1V1
• Mid4Layer: 3V3
• BottomLayer: Power traces, GND pours.

My questions are:

1. Am I not exaggerating with dedicating 3 layers to power? Should I rather have two GND layers (Mid1 and Mid4) and arrange two pours for 2V5 and 1V1 on one layer?
• TopLayer: Ethernet signals
• Mid1Layer: GND
• Mid2Layer: 2V5 + 1V1
• Mid3Layer: 3V3
• Mid4Layer: GND
• BottomLayer: Power traces, GND pours.

...or b) put that second GND layer on top of Ethernet signals (Eth signals moved to Mid1) so they are sandwiched between two GNDs? I would have to put vias then. I am not sure if it is a good idea.

• TopLayer: GND
• Mid1Layer: Ethernet signals
• Mid2Layer: GND
• Mid3Layer: 2V5 + 1V1
• Mid4Layer: 3V3
• BottomLayer: Power traces, GND pours.
1. Which voltage level plane/pour should be closer to ethernet signal traces? 2V5 or 1V1 or 3V3? Which one is more important to ensure a better integrity of ethernet signals. Maybe 1V1 should be over 2V5 and closer to GND?
2. Or are there any better ideas?

The phys are 2x DP83867 https://www.ti.com/lit/ds/symlink/dp83867ir.pdf. I think I could do the whole design in 4 layers but if 6-layer PCB is better then why not. The PCB is very small so price is not a significant decision factor.

Thanks for your feedback Marcus and Andy. I finalized the design with the following 6-layer stackup:

• TopLayer: Ethernet signals
• Mid1Layer: GND plane
• Mid2Layer: Other Signals
• Mid3Layer: 3V3 plane
• Mid4Layer: GND plane
• BottomLayer: Power traces, 2V5 pour, 1V0 pour, GND pours.

2V5 and 1V1 pours on bottom layer let me minimize the number of vias, as power decoupling caps (for the phys) are also on the bottom layer. (Phys are on top layer).

Other signals on Mid2 helped to keep other planes virtually intact. And I got a second GND plane, which will be placed between 3V3 plane and Bottom Layer.

So I ended up with a pretty classic 6-layer board stackup.

The datasheet of the PHY comes with a recommended stackup on page 127.

Use that instead of your slightly strange stackup; you don't need to put power on its own plane if it doesn't make layout simpler due to many distributed consumers, which you don't have.

Instead of adding unnecessary power planes, adding dedicated layers for high-speed signals to ease routing and thus allow for better routing at problematic points would make more sense, and that's exactly what the datasheet recommends.

• Thank you. Should recommended layer p.127/VDD be connected to IC/VDDIO3V3 or VDD2V5 or VDD1V0 or it doesn't matter? Jul 20, 2020 at 8:00
• I'd look into a split plane with the right supply where you need it! Jul 20, 2020 at 8:13
What do you do when you need to cross signal traces over?


I'd have top and bottom as signal layers. This way if you need to make a cut and mod it's on the outer layers and easily done. You can probably put many power traces on the signal layers too.

Then you could possibly get away with a 4 layer board with ground on the two inners with a bit of power routing (as needed) dipping in and out of those two middle layers.

That would be my first turn-to proposal and if it gets too complicated then you'll need to add another couple of layers.