# Amplifier design help

I am designing a two stage Amplifier for class, and I had asked for help before on the forum which helped a lot.

Input is a 1v sine wave. My design was for a 5 voltage gain however I am only seeing 2.4 volts across my load resistor.

I've ran through a number of calculations with the MOSFET common-source stage and I believe I should be getting a 5 volt gain, but I am not.

My current Design

Output across R8 in Blue

Input signal in Green

Here are the specifications I am designing to

Use one common-source stage and one common-collector (aka emitter-follower) stage

The amplifier must have an overall voltage gain magnitude of at least 5V/V during midband operation.

Generate an output signal > 3 Vpp

The input resistance must be > 100 kΩ.

Use a load resistance of 1 kΩ.

Use a single 12 V supply.

One of the amplifiers used need to be a MOSFET

At 27oC:

Low frequency cutoff between 100 Hz and 200 Hz High frequency cutoff between 50 kHz and 150 kHz

• Check the frequency response. At some frequencies you may get much closer to the gain you expect. Identify the limitations of each frequency selective part of the design and you will see which is the problem. As you haven't posted any specification for the required frequency response, it's up to you to decide how (or whether) to fix it.
– user16324
Commented Jul 21, 2020 at 12:22
• My mistake not posting the specification, I have edited Commented Jul 21, 2020 at 12:31

Because the circuit first_stage has resistor in the source, we can immediately ESTIMATE the first_stage gain as R2/R1, or 30 ohm / 10 ohm == 3X. That is the maximum possible. This initial estimate is also useful for bipolar stage (common emitter) design.

I view these circuits (FET, bipolar, vacuum tube) as two parts:

• (1) converting input voltage to output current, done via transconductor

with that output current driving

• (2) current_to_voltage converter, called a RESISTOR, which converts the current back into voltage.

Thus these simple circuits, providing voltage gain, are actually voltage_current converters followed by current_voltage converters.

There are two ways to compute the gain:

• Z_drain_parallel / Z_source_series

or

• Z_drain_parallel * Z_source_effective_transconductance

The books teach the 2nd, so I'll work some details in that way. (I prefer the first, and I suspect ANDY thinks the same way).

Now we add more circuit small_signal effects for a more accurate (using more phenomena) gain computation, which will only become a smaller value.

The voltage gain of the first stage, whether fet or bipolar, in small signal model, will be

• Av = R_convert_incremental_current_to_voltage * gm_effective

where gm == transconductance

and gm_effective == 1/ [ 1/gm_FET + R_discrete_source_to_ground]

Notice we are computing the gm_effective as 1/[sum of TWO resistors].

For the 2N7002, at 0.2 amp the "GM" varies from 1/10 ohms to about 1/3.2 ohms (datasheet gives this in milliSiemens, which used to be milli_mhos just inverse Ohms).

For this back_of_envelope design, convert the gm_FET to incremental_resistance of 10 ohms to 3 ohms, and add that value to the impedance of the components between the Source and Ground. Since the capacitor, as Andy indicates, is rather small, we'll ignore it.

So let us pick 5 ohms (somewhere between 10 and 3.2 as the 1/gm_FET and add that incremental resistance to the lumped resistor of 10 ohms. Total is 5 + 10 == 15 ohms. This is an estimate; we don't know the exact operating point; the relatively large value of 10 ohms lumped will serve to somewhat stabilize the gain, and reduce distortion.

At this point, we can instantly compute the maximum voltage gain as

30 ohms / (5 + 10) ohms ==== TWO.

But we are not done. Let us continue the refinement of gain computation.

Remember our mindset is:

• VoltageGain = Z_drain_parallel / Z_source_series

(which works just as well, given the same small_signal models are used, for bipolar or vacuum tube design), and I used "Z" as reminder there are AC effects (primarily capacitive) we are ignoring for now. [Given 30 ohms and 33pF is 1 nanosecond time constant, and any low_pass_filter action has a 159,000,000 Hertz F3dB corner --- also the 45 degree phaseshift --- and this F3dB is about 1Million X faster than the circuit of interest, we'll let "R" be our method.]

We have refined the Z_source_series (remember, we simply ADDED the incremental resistive effect in the source; you can use calculus and the Taylor Series model of FET gm or of bipolar gm, to compute the incremental resistor).

Now let us refine the Z_drain_parallel (which also Z_collector_parallel for bipolar, or Z_plate_parallel for vacuum tube).

What is the function of Z_drain_parallel? That function is to convert the current flowing thru the transistor, back into a voltage.

The R_convert_incremental_current_to_voltage is the parallel combination of these resistors:

• R_drain_to_VDD, which you picked as 30 ohms

• R_load_next_stage, which is >>> 30 ohms [1K || 1K || (beta * Rload) ]

• R_slope_of_FET_I_to_V_plot (called EarlyVoltage Effect in bipolars; and "lambda" effect for FETs), which at << 1 amp for the 2N7002 appears FLAT in the plot of output I_V behavior for Vds of 5--8 volts.

Summary of these THREE in parallel ----- just 30 ohms.

========================================

By the way, your 2nd stage, the emitter_follower buffer AKA common_collector is rather well designed. The current is about 10mA, so the Rout is about 0.026/0.010 == 2.6 ohms (small signal) which will drive 1,000 ohm load rather well, at least for small signals. You may see lots of distortion, even clipping, for large voltage swings. The current of 10mA, times 1Kohm, is 10 volts, thus there is possibility for healthy output swings.

Your time constants need refining, as ANDY indicated to you in his answer.

You are learning a lot, with numerous interacting device parameters and with series impedances and parallel impedances(OK we just used Resistances, at this low frequency --- well below 159,000,000 Hz).

But this is a REAL WORLD circuit, teaching you a lot. Hang in there. Chat with other students. Or ask the TA for opinions.

==========================

And read the answer by rpm2718, on setting the operating point, the "Q" point.

Your input frequency is 250 Hz - I see roughly a time-base of 4 ms. At this frequency, the 100 nF (C3) has an impedance of 6366 ohms and is a pointless addition in parallel with R1 (10 ohms). That's my first observation. There's no point fitting it either.

My second observation is that at 250 Hz you will not achieve a gain higher than three for this circuit. The gain is roughly defined as the ratio of R2 (30 ohms) to R1 (10 ohms) so, three is the best you might get. I'm still saying don't fit C3 too unless you want some strange increase in gain at the higher end of the spectrum.

My advice - increase R2 to something like 60 ohms and see how it pans out. You might need to adjust the gate input bias resistors to keep the quiescent voltage at M1's drain roughly mid rail of course.

What did you do to overcome the massive time delay at power-up caused by C1, R2 and R4 BTW?

Some good analysis about gain is already in the answers given. One additional thing to watch out for your quiescent current and power dissipation in the MOSFET. From the datasheet:

These values vary a bit from one manufacturer to another, but this one, from ON Semiconductor, shows max continuous drain current of 115 mA for the 2N7002. Your quiescent drain current is exceeding that. Your quiescent power dissipation needs to be calculated as well, which could become a problem if your source-drain voltage were large enough. This probably won't be the case, but checking it is part of the design process.

To lower the quiescent current, you need to raise R1, while setting R2/R1 according to gain requirements. Then you need to make sure that your output impedance from the first stage is low compared to the input impedance of your second stage, which may suggest that you increase R5 and R6 a bit.

Finally, to get the higher gain and 3 Volts peak-to-peak swing, you are probably going to have to lower your quiescent gate drive voltage a bit as well or else the drain resistor will drop the quiescent voltage too much. This will of course affect the choice of R1 and R2, so you may want to start by doing this first.