# Does VHDL allow port mapping of a single bit output to multiple bits driven to same value, in one line?

For this hypothetical entity:

entity test is
port (
a_out: std_logic
);
end entity;


The a_out must drive three signals to the same value where the test entity is instantiated. Now one can create an std_logic signal and port map it to a_out and then drive the other three signals from this port mapped signal. Something like this:

signal bit_signal : std_logic;
signal x : std_logic;
signal y : std_logic;
signal z : std_logic;

test_i: test
port map (
a_out => bit_signal
);

x <= bit_signal;
y <= bit_signal;
z <= bit_signal;


It would be great if the intermediate bit_signal is not required and the a_out can directly drive the signals x, y, z doing something like this:

test_i: test
port map (
a_out => x, y, z
);


I don't think VHDL 2008 allows this, I cannot say anything about the VHDL 2019 though.

• Why do you even need to split up a duplicate signal like that so it has identical names? You already need an intermediary signal anyways to connect port-to-port and you can just run that one everywhere. If you need to perform an operation you just read the signal wherever the operations are done and write the outputs separately. In what case do you need three identical signals to have different names? I can think of none. Also, a comma under a port map moves to the next signal to be assigned so I would assume no. – DKNguyen Jul 21 '20 at 18:17
• @mbedded What you posted was a signal assignment. OP is asking about a port assignment which uses => – DKNguyen Jul 21 '20 at 18:44

You could try using alias, something like this:
signal x: std_logic;