# Frequency divider circuit of a factor of arbitrary number

We know that using T-Flip Flops in a cascaded manner(something like ripple counter) allows us to divide the clock frequency by a factor of $$\2^{n}\$$ where $$\n\$$ stands for the number of flip-flops. Now, Suppose I want to divide my original clock frequency by a factor of 3 or by 9? What can I do to achieve this?

My progress: Suppose we want to divide the given frequency by a factor of 6. Then, I thought that we can achieve our task by connecting the counter circuit and then adding some combinatorial circuit to change the clock only when 3 counts are done. This way whenever 6 counts are completed, one output cycle will complete.(Look at the circuit below): But how do we do when we want to divide the clock frequency by a factor of 3 or 5 or 9?

• If you don't care about duty cycle, just toggle after 2 counts, then after 3 counts, then 2 counts again and so on. This will divide the frequency by 5. For this, you will need not only a combinatorial circuit, but a memory element also (a flip flop?) to keep track of whether the current count limit should be 2 or 3. – AJN Jul 22 at 3:33
• Suppose we want to have a factor of 3. Then? – Puneet Jul 22 at 3:39
• Like whenever three clock cycles complete, my one output cycle will complete. – Puneet Jul 22 at 3:39
• For three use 1 count and 2 count alternately ? – AJN Jul 22 at 3:41
• Okay. But I think we won't be able to maintain a duty cycle of 50% then. Right? – Puneet Jul 22 at 3:42

Use added logic to capture counts as they appear at the binary counters outputs. The LSB is 1 if high. The weight of the bits is 1, 2, 4, 8 for a 4 bit counter. A count of 9 means 1 and 8 are high, 2 and 4 are low. Use and or nand gates on these pins to reset the counter each time it has a count of 9, or a count of 8 if asynchronous reset, as 0 is part of the count.

As long as the clock pulse is running it will repeat the same count endlessly.

Because 0 is part of the count, the counter will have one more state then the counters value.

• This is correct. But I wanted to divide my clock frequency by arbitrary number. From your explanation. From what I understand, your suggestion would yield an answer which would have double the required time period. – Puneet Jul 22 at 3:45
• For example I want my output to have a duty cycle of 50% and when three clock cycles complete, then one output cycle should complete. – Puneet Jul 22 at 3:48
• To make a counter have an arbitrary value feedback is mandatory. If you have time constraints then double speed the clock. – VTNCaGNtdDVNalUy Jul 22 at 3:49
• Okay. Doubling the speed of the clock will work(given we can do that). By the way, I am new to electronics, what is arbitrary value feedback? – Puneet Jul 22 at 3:51
• 50% duty cycle is impossible for odd numbers, unless you use a FF to divide by 2 to get 50%. – VTNCaGNtdDVNalUy Jul 22 at 3:51

Your flip-flop divider is creating a binary counter: the input is the one's place, the first FF gives the next binary digit, etc.

The key is that this type of counter resets automatically, e.g. after 16 cycles using 3 FF's (4 bits). You can also reset the counter earlier to create an arbitrary divider; if you enable a (synchronous) reset when that counter has a value of N-1, the top bit (that changes) will yield a rising edge every N cycles.

Note that this output will not have a 50% duty cycle, unless N is a power of 2. You can improve this with some additional decoding, outputting a 1 (only) when the counter is N/2 or greater. If N is odd, you will need something like a PLL to achieve 50%.

Question

How to divide frequency by an arbitrary number? 