The Xilinx App note XAPP052 "Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators" shows a method on how to use LFSRs to get random bit sequence of maximum length. I expected this to be a chain of registers similar to one used for CRC checks where we use feedback XOR gates to generate the random bit sequence. However, this appears different.
There are few things that I am trying to understand here:
- How are they implementing a 32-bit LFSR using 2 16x1 SRAMs and 4 DFFs? Shouldn't it be 32 DFFs with some taps using feedback? The inclusion of Synchronous RAM blocks is confusing.
- What would be the structure to implement 12 bit and 16 bit random bit sequence?
- In Table 3 it gives the "XNOR form" and the length of the chain used to generate the random bit sequence. Is there a way that I might carry out simulation using this information in C language or otherwise?
The mixture of DFFs and Synchronous RAM blocks is confusing me as it does not match a simple shift register chain with XOR gates in feedback as used with CRC checking hardware. The reason I expect this to match CRC hardware is that both have concept of a polynomial that decides where we tap to get the feedback bits.
Edit: I would be grateful if someone can clarify the relationship between Tables 1 & 2 and the Table 3. Why are there only 4 DFFs each time and they are providing address into some RAM blocks? That is now how shift registers work.