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I am checking out for dual-inline packages for my chip (which I want to insert in DIP) and I came across some products from Analog Devices, Texas Instruments and NTK Ceramics. However, NTK Ceramics have dimensions for the chip Die. But Analog devices and the Texas Instruments doesn't have any information about the Die for DIP. Are the DIPs from Analog Devices and Texas Instruments just only programmable without any option to ınsert our own chip into the DIp?

You can find the picture of the datasheet of 24 pin DIP of Texas Instruments (İt doesn't have any picture of the Die) and Also you can find the other picture of DIP from NTK Ceramics which has die information shown clearly

Texas Instruments DIP NTK Ceramics datasheet

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    \$\begingroup\$ NTK Ceramics builds DIP packages for integrators of custom silicon. TI and Analog Devices obtain and/or build DIP packages for their own chips, and as such, the die size is not a datasheet parameter. If this doesn't seem to be the case, please link to the specific datasheets and products you are discussing. \$\endgroup\$ – nanofarad Jul 23 '20 at 23:55
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    \$\begingroup\$ I'd be amazed if TI or AD would build you a custom chip unless you're ordering millions of them (and maybe not even then). That's just not what they do. \$\endgroup\$ – brhans Jul 23 '20 at 23:57
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    \$\begingroup\$ TI, AD, and other IC makers provide descriptions of the packages they use for their ICs for the convenience of their customers in using the ICs. I would not expect them to sell empty DIP or other packages to end users. \$\endgroup\$ – Peter Bennett Jul 24 '20 at 0:08
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    \$\begingroup\$ If you're asking about the maximum die cavity size internal to the DIP package itself (as opposed to the "silicon chip" dice sales from TI/AD/etc.), that's likely proprietary information. If you are in contact with a company that sells empty DIP packages or that makes the internal leadframes, their applications/sales team may be able to share those cavity size dimensions. But only the outside of the DIP package is standard, the inside dimensions are not standardized. \$\endgroup\$ – MarkU Jul 24 '20 at 0:38
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    \$\begingroup\$ If you're targeting a DIP today for a custom chip, then you are doing it wrong \$\endgroup\$ – Chris Stratton Jul 24 '20 at 0:48
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Often the die cavities can be selected, based on the aspect ratio (length and width of the silicon chip) and the silicon area.

You want to nearly FILL the cavity, for good heat removal, since most of the heat (at least for plastic) has to flow FROM the silicon THRU the plastic and then TO THE LEADFRAME.

Thus for plastic, a small die in a large cavity is BAD THERMAL DESIGN.

The black epoxy has 200X the thermal resistance of silicon and copper(the lead frame often is alloy of steel and copper).

And those gold bond wires are about 10,000 ° C per watt, per milliMeter of wire.

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