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In a DDR memory, during a read, output data from the DDR is aligned on the strobe. There is one strobe per 8-bit:

  • UDQS/LDQS for a 16-bit-wide DDR
  • DQS[0-3] for a 32-bit-wide DDR

Is there any significant delta between the strobes of the same DDR chip? 'Significant' means: can I use one strobe for all the bit? I have a custom-made DDR controller in a FPGA and I would like to use one strobe for the entire data set.

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  • \$\begingroup\$ How confident are you about the source of the memory? If each 8 bits comes from a separate chip, expect skew between them. Are you driving them at the nameplate rate? If you are underclocking them by a factor of 4, your timing budget has more room for error. \$\endgroup\$ – user_1818839 Jul 25 '20 at 9:35
  • \$\begingroup\$ @BrianDrummond, obviously, it's only one DDR chip. I thought the question was clear enough. I'm editing it. \$\endgroup\$ – gregoiregentil Jul 25 '20 at 15:24
  • \$\begingroup\$ @DaveTweed, Thank you. You can put your comment as an answer. So basically, at the 'exit' of a 16-bit DDR chip, the two balls or pins [UL]DQS are in sync or quasi in sync. Multiple DQS is provided more for convenience of routing (or if you use [UL]DQM). \$\endgroup\$ – gregoiregentil Jul 25 '20 at 15:30
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The timing budget on a DDR memory interface is very tight to begin with. If you use only a single strobe, you'll have to carefully length-match all 33 traces as a group to minimize skew. If you use individual strobes, then you only need to length-match groups of 9 traces at a time. The matching between groups can be a little more relaxed.

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