My question is: If I have properly set VGS to prevent MOS from turning off, then if we biase a MOSFET with a constant current source, how can we conclude that it is working at saturation region? How large should this current be? How come that it will automatically work in saturation region? Why not triode region?
A circuit is really understood when the basic idea behind it is seen (as they say, "to see the forest for the trees"). That is why, first I will reveal the philosophy behind this topology and then will show how it is implemented in the specific circuit.
In the classic circuitry, such an arrangement is known as "cascode". Conceptually, it can be considered as two complementary "sources" connected to each other; one of them is a voltage source and the other is a current source.
From another viewpoint, one of them can be thought of as a "dynamic load" for the other. So, we can consider this arrangement as a voltage source loaded by a current source… or as a current source loaded by a voltage source. They provide ideal load conditions for each other as follows:
When the voltage source tries to increase the voltage, the current "source" increases its resistance thus "helping" the voltage source. As a result, the voltage source "has the feeling" that there is no load connected (open circuit).
When the current source tries to increase the current, the voltage "source" decreases its resistance thus "helping" the current source. As a result, the current source "has the feeling" that it is short circuited.
We can think of this arrangement as two interacting systems with negative feedback. Each of them keeps up its quantity but always there is a equilibrium in this aggregate.
In the OP's picture above, the voltage source is implemented by M1 MOSFET acting as a source follower. The current source is usually implemented as another MOSFET connected in a common-source stage with constant input voltage.
Varying the current. To control M1, first we have to apply some voltage VG to M1 gate. Then imagine we increase the current I1 (figuratively speaking, the current source "pulls down" M1 source). M1 source voltage tries to decrease but since the gate is fixed the gate-source voltage increases. M1 senses this disturbance and begins increasing its drain current until the equilibrium is restored. Finally, M1 adjusts its drain current equal to I1. In this way, we can set the desired biasing (quiescent) current.
Varying the voltage. The OP's circuit is a source follower where VG is the input voltage. Let's, for concreteness, increase VG. In the first moment, M1 source voltage does not change and the gate-source voltage increases. M1 senses this "disturbance" and begins increasing its source voltage until the equilibrium is restored. Finally, M1 adjusts its source voltage almost equal to VG.
The source follower (M1) is an analog "circuit" with negative feedback; so it is not so dependent on the region (saturation or triode). Usually, the input voltage VG does not reach VDD and M1 works in the saturation region.
When an NMOS is biased for constant current operation, which can provide enormous gain, the circuit is grounded source, bias on the gate, and the current source in the drain.
And in that case, some operating_point feedback is needed, to set the Vds near VDD/2 for good output voltage swing.
In a properly designed operational amplifiers, the negative feedback achieves that purpose.