So this is my first question here.

I am reading this book, "Digital Electronics & Computer Design - By M.M. Mano". While I was reading the Sequential logic and flip-flops, I found this:

The feedback path between combinational circuit and memory elements(flip-flops) in a sequential circuit can produce instability if the outputs of memory elements are changing while the outputs of the combinational that go to flip-flop inputs are being sampled by the clock pulse.

I didn't understand this statement. So I googled and found a similar statement at circuitstoday.

If a clock pulse is given to the input of the flip flop at the same time when the output of the flip flop is changing, it may cause instability to the circuit.

I tried to get my head around this but didn't come up with any idea that gets me peace. I'm confused especially with this "the outputs of memory elements are changing or when the output of the flip flop is changing. What does it mean? Because the output of a flip-flop will only change if there's a change applied on input signal. It will not change by itself.

So I came up here. Please help me with this context. Any help would be appreciated.


1 Answer 1


It means that the input to flip flop must be stable for some amount of time before (setup time) and after (hold time) the clock edge. If the input is changing when there is a clock edge, it cannot sample it reliably as logic 1 or logic 0, and depending on what kind of paths the clock and data propagates inside the flip flop, there might be a short glitch on the output, or the inverting and non-inverting outputs could output same data while they should output complementary data.

The output of the flip flop will update to new state only after some propagation time, so if there is a feedback from flip flop output back to input, it means that the clock edges must not happen too rapidly, so that the output has been stable for enough time to satisfy the input setup time, and the flip flop output must not change too early to satisfy the input hold time as well.

  • \$\begingroup\$ i.e. if previously there's an input applied to flip-flops, then we have to wait at least for the time equal to propagation delay of the circuit to give new input? Like if we have a combinational circuit, which takes, a, b & c as inputs where c is feedback from memory element and outputs x & y, where y is the input to flip-flops. \$\endgroup\$
    – Shubham
    Jul 26, 2020 at 12:02
  • \$\begingroup\$ Then in the first clock pulse, when y goes to flip-flop, there should be enough time(or we have to wait for the time equal to) to propagate signal y through the flip flop and through its feedback path, back to the combinational circuit? \$\endgroup\$
    – Shubham
    Jul 26, 2020 at 12:09
  • \$\begingroup\$ If this is the matter then there's another confusion. i.e. the combinational circuit will not work until all the three a, b & c inputs are available. So no matter if user supplies a & b to the input terminal of the combination circuit, it'll only work when the c will be present. \$\endgroup\$
    – Shubham
    Jul 26, 2020 at 12:14
  • 1
    \$\begingroup\$ Anything can happen like I already explained. Glitches or wrong output. It's called metastability, it's not a stable state. When the clock edge comes, and if the data input voltage is halfway between logic 0 and logic 1, there is no way to tell if the chip interprets it as logic 0 or logic 1, and if every part of the chip interprets it as being the same logic level, or will some parts of the chip think it is logic 0 and some parts think it is logic 1. I'ts really the same as taking a photo of a football, and if you ask a bunch of people whether the ball is moving left or right, or not moving. \$\endgroup\$
    – Justme
    Jul 26, 2020 at 16:01
  • 1
    \$\begingroup\$ Or actually, that explained when it was transitioning. See, a flip flop is also just bunch of logic gates one after another to make a flip flop, so it will take time for the data and clock to propagate through all the logic gates inside the flip flop. So if a clock comes too early, the data may not have propagated through all gates inside the flip flop and the data can be still transitioning at some gates that are already clocked. \$\endgroup\$
    – Justme
    Jul 26, 2020 at 16:04

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