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I am currently reading about caches and how they are used in Computer Science. The explanation of how the cache is always up to date with the actual memory is understandable as long writing and reading can only be performed through the processor.

But modern architectures use DMA, which means data can be written to the memory, without being transported to the processor.

So how cache coherency is ensured, when the cached memory block is used through DMA in modern architectures?

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  • \$\begingroup\$ Even though data doesn't pass through the process, the initial DMA request is processed by the processor. \$\endgroup\$
    – AJN
    Jul 26 '20 at 12:17
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    \$\begingroup\$ @AJN Often, but not necessarily so, no. \$\endgroup\$ Jul 26 '20 at 12:17
  • \$\begingroup\$ Wikipedia on cache coherence. It agrees with @MarcusMüller \$\endgroup\$
    – AJN
    Jul 26 '20 at 12:18
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AJN pointed out, that in many cases, the entity controlling the DMA controller is the same as the entity with the caches - namely, the CPU. In that case, of course, one can write software that first flushes the affected cache regions before initiating DMA transfers.

However, that's not always the case, and when there's multiple CPU cores involved (which is rather the norm these days), you need coherency protocols and measures.

This can involve "snoop" units that simply listen in on cache controllers, and DMA engines.

But that can also simply mean that you need to be careful with the memory your devices can DMA to and from. In fact, this is a very practical problem e.g. in things like the Xilinx Zynq; solutions involve not writing into the "proper" RAM but directly into cache, if you know that the data is going to be used very soon, anyway, and hacking together memory barriers for other cases.

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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$
    – Voltage Spike
    Jul 27 '20 at 20:15

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