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I am wondering why don't we make processors such as CPUs with 1000s of stacked layers to make use of space in the third dimension now that we have three-dimensional transistors. To be clear I'm referencing making something of a rectangular-prism shaped processor.

To be clear there's a vast amount I am not aware of when it comes to processor manufacturing, I am not an electrical or computer engineer, but I am very curious. I am aware of the heating problems this would cause considering an even more dense packing of transistors and the manufacturing problems considering you would have to laser etch through so much silicon, but unlike enlarging the size in width and height there wouldn't be problems with making the most of the circular silicon wafers, and unlike with that you would be keeping the parts very close which means it wouldn't slow down the speed of the electricity getting from one part of the processor to the other because the processor already has 1000s of transistors stacked horizontally and vertically.

I am curious if you could solve the heating problems by laying down thin intermittent heatsinking layers, while keeping the vertical throughput. And fix the manufacturing problems partially by using separately etched wafers every 10 layers or so. Could this be possible or are there lots of problems I'm not thinking of (and I'm sure there are)? Thanks.

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    \$\begingroup\$ How exactly do you imagine these "thin heatsinking layers" to work? A heatsink doesn't really "sink" heat as in "destroy" it, it just conducts it away. A layer inside the stack can only help by conducting heat to the sides of the die, and that's a long way to go (at least several millimeters), making it horribly inefficient. \$\endgroup\$
    – TooTea
    Jul 27 '20 at 10:08
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    \$\begingroup\$ Why dont we make 1000 layer cakes? After a certain number of layers it starts to fall apart, cant fix it with icing. \$\endgroup\$
    – old_timer
    Jul 27 '20 at 14:36
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    \$\begingroup\$ @old_timer Your example is ill-chosen: en.wikipedia.org/wiki/Mille-feuille \$\endgroup\$
    – James_pic
    Jul 27 '20 at 16:34
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    \$\begingroup\$ I didnt see any 10-20-100-1000 layer anything, even when you fold pastry many times it does not make for a consistent layer, esp after processing (baking). In both cases each layer has inconsistencies that amplify on each subsequent layer (see answers below) if you could solve the heat problem then you have the stacking problem. Just like a cake. One 50 layer cake for prize/award purposes sure, but mass produce them, not so much. Certainly not a 1000 layer. \$\endgroup\$
    – old_timer
    Jul 27 '20 at 17:09
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    \$\begingroup\$ then there is the cost as well, masks are a big part of the cost of a chip, if a small number of layers is a handful to tens of millions then 1000 layers is....more than the company is worth. And thats if you could find equipment to do this. its a silly question. we are just making multi chip modules common beyond high end products. If your process is half the size of the prior that is about the same as stacking twice as high. so it is not like they arent doing anything to increase density and performance per "chip" \$\endgroup\$
    – old_timer
    Jul 27 '20 at 17:13
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The two killer reasons are yield, and heat.

Yield. Every time you do a process step, you get less than 100% perfection. Let's say you get 99% perfection per step. In a process with 20 steps, you would be down to 82%. In a process with 1000 steps, you would be down to 43 ppm, 43 successful builds for every million wafers started.

Heat. Our existing designs are already limited by how fast we can extract heat from the bottom of the die. So neither the opportunity to generate more heat, nor the opportunity to generate that heat further away from where it can be dissipated, is of any real use to us.

Those said, there are some devices building up into the 3rd dimension, bonding several finished wafers together, which mitigates the yield issue. Those stacked wafers tend to be memory, which don't use anything like the power of a CPU, which mitigates the heat issue.

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    \$\begingroup\$ You could stack pieces that were made separately. The real problem is heat. \$\endgroup\$ Jul 27 '20 at 18:59
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    \$\begingroup\$ Flash is often die-stacked, using 16 or more dice stacked together. Here heat is less of a problem as the extra layers are for capacity - you're only accessing one layer at a time. That's less easy to do for CPUs where you expect them all to be busy at the same time. \$\endgroup\$ Jul 27 '20 at 22:21
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    \$\begingroup\$ @Ethan722 A high-end CPU has well over a billion transistors with over 20 cores. What engineers want is not stacked CPUs but a extra layer of dram or flash, even as separate dice. What you propose will not happen in our lifetime. Extreme density ALWAYS creates too much heat to be viable. \$\endgroup\$
    – user105652
    Jul 28 '20 at 0:17
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    \$\begingroup\$ Our current computing limit is very rarely at CPU processing power. Data access is the primary bottleneck, and has been true for decades. For a typical computer, upgrading from HDD to SSD and upgrading RAM gives the biggest bang for the buck. There is a reason why advertisers point out the "BIG HERTZ" of CPU and gives you a computer with 2-4 Gb of RAM; the system will degrade very quickly and you will think you need a new one, when a $100 RAM upgrade will make it last another 5-10 years. \$\endgroup\$
    – Nelson
    Jul 28 '20 at 1:27
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    \$\begingroup\$ @Ethan722 (not an EE expert just a tech head passing by) The heat dissipation is a much bigger issue than your comment makes out. A single AMD Threadripper 3990x can put out around 280W of heat. If you could somehow stack them 100 high, you are now talking about dissipating (280W * 100) = 28KW of heat. \$\endgroup\$ Jul 28 '20 at 8:35
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Heat removal is the issue.

Already some chips have higher energy density than a nuclear reactor.

Consider a hair_drier ---- 1,500 watts with a air_blast fan to cool the tungsten coils. And the coils glow dull red.

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    \$\begingroup\$ Power density, surely. That means they also have higher power density than the sun, right? \$\endgroup\$
    – user253751
    Jul 27 '20 at 9:44
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    \$\begingroup\$ Apparently the power density of the sun is not really that impressive \$\endgroup\$
    – ManfP
    Jul 27 '20 at 17:19
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    \$\begingroup\$ @ManfP Yeah, but it can go 10 billion years on a charge, so that's something... \$\endgroup\$
    – J...
    Jul 27 '20 at 18:12
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    \$\begingroup\$ @J... which is handy because every time you go near it with a usb charging cable it melts. \$\endgroup\$
    – Sirex
    Jul 28 '20 at 1:42
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    \$\begingroup\$ @user253751 Your own body has a higher power density than the sun. \$\endgroup\$
    – Mike Scott
    Jul 28 '20 at 5:57
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Transistors are far easier to make on the bottom layer, because the traditional structure involves "n-well" or "p-well" structures.

Also: Planarisation.

The bottom "substrate" layer is mechanically polished to a very high degree of flatness. Subsequent layers on top are etched and deposited, but each time is less than perfect. There is a risk of errors adding up causing features not to align properly on a "lump" in the surface.

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But what would you get from that?

  1. The number of transistors per mm² of mask you get would still be the same, you'd just have more masks
  2. Alignment of multiple masks is way harder, the more masks need to be aligned.
  3. You'd probably need multiple extra interconnect layers for each extra transistor layer
  4. Making a connection between layers is more effort than making a connection within a layer.
  5. Heat dissipation would be worse
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    \$\begingroup\$ Some computers, e.g. en.wikipedia.org/wiki/Titan_(supercomputer) have used 3D connection topologies so the distance between many nodes is less. 1023 cores on 50μm wafers stacked on top of each other would have far less distance between them than a 2D grid of 32 cores per side, enough to share GHz clocks etc. \$\endgroup\$ Jul 27 '20 at 16:28
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There are 2 main reasons:

  1. Heat dissipation - this requires contact surface. That surface transfer heat from the CPU to the cooling system. If it's 3D, it becomes extremely hard to evacuate heat from the under-layers as the surface-of contact would be significantly less than needed to sustain the thermal transfer.

  2. Yields - they are low in many cases anyway. When nVidia was trying the GTX 285/295s they had initial yields of under 2% and after process stabilization they were still under 10%. That meant they had to cut-off parts of the chip to make lower class cards out of the remaining good portion. And that was with a standard 2D process that was just over-sized. Trying to put anything in 3D would have even lower yields if we were to ignore the heating part.

In addition, adapting the fab process completely (assuming everything else is fine) is not something many would be willing to just go forward with while there's more to be had from the current tech.

HBM Memory managed to do things in stacks. It's not really 3D, it was called 2.5D due to having only a few layers and it is an expensive solution. The package size is large, and it comes with thermal management challenges (even if the heat generated is significantly lower compared to CPUs). The advanced chip packaging technology that vertically connects DRAM chip dies using electrodes that penetrate the microns-thick dies through microscopic holes came to the rescue in this case.

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  • \$\begingroup\$ HBM-- a lot of nice stacking/interposer images available online. Also not mentioned in other answers is NAND Flash memories-- these have gone vertical in a big way, with 128 cell layers stacked vertically. Since only 1 of the 128 might be active, the heat's not an issue. \$\endgroup\$
    – stevesliva
    Jul 28 '20 at 16:30
  • \$\begingroup\$ NANDs are not continuously processing with most of theirs "cells" so that can be quite fine from a heat perspective. \$\endgroup\$
    – Overmind
    Jul 29 '20 at 8:06
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A wafer passed all 999 steps but failed on the 1000th step -- Ouch. It also take time and many steps to create a layer: photo-resist/developer/scanner/etch/clean/SEM and etc...That's why manufacturers try to increase the density rather than stacking. For example, building a single story house is different than building a 100 story skyscraper. You can't just stack a house over and over because it'll collapse after a few stories.

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The thing is, the scientists of today don't understand why things get hot even when specific energies are applied to achieve a specific result.

It's all down to quantum energy potential to achieve the flipping of a transistor (over-loaded/under-loaded) which they can't perfect because of universal forces that act upon your chip even though it's shielded, forces are still interacting with these potentials, these interactions are best guess at best and don't seem to factor into their thinking, energy waste is emitted from all axis of geometry and not straight along the path of least resistance, also the harmonics of the substance the energy is trailing through is not perfect geometrically but that's just another issue.

I digress, 3D stacking would require intermediate waste collectors that absorb the waste energy from the chip instead of passively extracting the waste.

Think of each transistor as being overloaded by fluctuations over time that causes an emission like a power station when breaking a spark gap, the energy has to go somewhere before the connection is broke on the first connection but since it's not, the transistor causes an emission that radiates the energy in the form of heat due to the spontaneous crash of waste energy that tries to trigger the transistor but can't and so it's reflected or the energy just keeps colliding with the geometry of the cpu until it's out of energy and each time it reflects it breaks down giving off heat..

The trick is to have trickle-down processing like a stack of cards in a triangle, each nose in that card pyramid is tracked from beginning to end and the remaining energy would be dumped to another processor which is just there to FILL THE DEMANDS of absorbing the waste energy if any.

The reason why you want another processor to pick up the waste energy is because the energy needs to dissipate and work naturally, the path of least resistance happens on many scales and forms, timing is very important, the faster your clock the more time you have to play with the energy that you have.

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  • \$\begingroup\$ I would love to hear from the person who down-voted my comment and try to explain any differently and if why they down-voted at all but i hardly doubt I will hear from them. \$\endgroup\$ Jul 29 '20 at 14:19
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    \$\begingroup\$ I'm not the one who downvoted you but there are a few things in your answer that just don't make sense or are plain wrong. Energy crashing into transistors? Energy failing to trigger transistors? Energy breaking down? And heat coming from that? People today don't understand why things get hot? Clocking faster reduces energy consumption? \$\endgroup\$ Jul 29 '20 at 15:08
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    \$\begingroup\$ What are "waste collectors"? This isn't a standard EE term and you never explain what they are or how they work. Same for "trickle down processing". A good answer should be understandable to others by using standard terminology where possible and defining terms where not. \$\endgroup\$ Jul 29 '20 at 15:27
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    \$\begingroup\$ Well, the answer is incoherent. If it's trying to say something, it's trying to say too much with too little. \$\endgroup\$
    – DKNguyen
    Jul 29 '20 at 23:21
  • \$\begingroup\$ user1850479 Waste collectors are connections between the load being taken and where the load is absorbed to trigger a flIp in a transistor. The waste collector gate should absorb enough energy to create the flip and dump the rest back into the power supply otherwise the waste energy turns into heat. \$\endgroup\$ Oct 27 '20 at 16:08

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