# Approach to an unknown orthogonal Beta Signal with a known alfa in single phase dq transformation

I am trying to implement a PLL controller to the MCU for tracking single phase line voltage . I get samples via an opamp circuit with a DC offset and the samples' raw values vary between |-244 , +244| when removed the DC offset . The key problem I'm trying to overcome is that the DQ transformation needed in the design requires a made up second orthogonal signal (Beta) other than the alpha . As far as I read the papers written for single phase PLL implementation , we need a 90 degrees time delay of the original signal , so it is our alpha .. Let's say an instant adc value is 128 and that is the alpha , so how to create an imaginary orthogonal Beta signal using that ADC value ? What I need for a park transformation is the alpha and beta , I got the alpha but what is the beta ?

D = Alpha*cosTETA  + Beta*sinTETA
Q = Beta*cosTETA - Alpha*sinTETA


Beta = ?

Sounds like you seek to phase_track a signal, for which you have some inphase and some quadrature information.

And you need to preserve the polarity of the information, so you can have a Negative Feedbac control system instead of a Positive Feedback system.

Show all your information_extarction maths, and the sensor input to the system.

Then think about how to preserve the needed polarity of the control output.

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If you want to phase_track a sinusoid, then yes you can generate a quadrature signal using a differentiator. This will be noisy.

If you want to phase_track a non_sinusoid, you need to decide which edge to align with, and use a phase_frequency digital_phase_frequency circuit; this has 2 FlipFlips, a ORing gate, and (usually) a tiny delay needed to ensure healthy RESET pulse behavior.

• Thank you for your kind answer .. I have all PI regulator, LPF block for the PI output stage and control routine completely ready in my mind but I only have difficulty of generating the imaginary orthogonal Beta signal to complete the park transformation. If I assume directly my alpha equals the adc sample , what would my beta be ? Should I get this beta usign inverse park transformation ? Or directly say Q*sinTETA or what .. This is the part that digs my mind ... Commented Jul 28, 2020 at 5:06
• I succeeded the PLL algorithm by taking the beta as 90 degrees delayed ADC value from an ADC buffer which is continuously filled in a periodical interrupt routine . But there is still a question mark to create that imaginary Beta using some other equation like reaching Beta value using d , sinTETA etc .. But How ... Commented Jul 28, 2020 at 8:49

Generating a quadrature signal from a direct signal can be accomplished with a SOGI (Second Order Generalized Integrator). The conceptual schematic is this:

V1 generates the input and the two integrators enclosed in a feedback loop (an electronic ouroboros) generate the quadrature signal. V2, through the two multipliers, provides the frequency. Here, I chose to use f, frequency, as opposed to ω, pulsation, in which case the two time constants for the integrators would have been 1. The gain sets the damping, 1.41 (√2) providing a good compromise between the bandwidth, flatness, and response time. The latter is what matters more in the case of PLLs. This is usually achieved in software, and multiple SOGIs can be used, if needed.

The transfer functions for each output are:

\begin{align} D(s)&=\frac{ks}{s^2+ks+\omega^2} \\ Q(s)&=\frac{k\omega^2}{s^2+ks+\omega^2} \end{align}

so you can see that there is a lowpass and a bandpass, whose magnitudes coincide at ω and their phases are 90o appart (k is the gain block):

• Hmm, I think the transfer functions, due to the way I drew the schematic, need to have $ks$ replaced by $k\omega s$. If the frequency was fixed, then the t.f. would have been as they are now, but the external frequency allows the SOGI to be used for an adaptive block in PLLs. Commented Jul 28, 2020 at 17:28
• So what I need is transforming these s domain arguments to Z domain and get the coefficients then apply it to my pll routine ? Commented Jul 28, 2020 at 18:19
• I suspect that even a properly sampled backward Euler would work, but, of course, it depends on how precise your requirements are. Ultimately, if you're feeling adventurous, you can implement this the analogic way, though the multiplication is a lot easier in software. Otherwise it's either an analogic multiplier, or some clever JFET used to change the integration time constant. Commented Jul 28, 2020 at 20:25
• Is it possible you could give an code example ? Let's say you have only an adc value and take that as Alfa ...How would you interpret the Beta simply ? (or your difficult way) , I need your point of view .. Commented Jul 29, 2020 at 16:58
• Would this help? Commented Jul 29, 2020 at 19:03