We are designed and printed the PCB of the stm32f103c8t6 blue pill board as per stm rules.. After fabrication and assembly finished, we connect the board to Keil software and device detected and the program also uploaded perfectly... we faced some problems listed below...

1.ADC value varied in the difference of ( + or - 50 ) ..total range is (0 - 4095)

2.we crossed checked the program with stm bluepill ( amazon board )..it works fine...but our pcb boardADC value varied...it means program is good and hardware is something wrong.

3.we removed the crystal oscillator (8Mhz) in our board..ADC value works fine in our board.

Anybody kindly helps me with this problem..?

I have attached below the schematic layout image..


stm32f103c8t6 layout

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    \$\begingroup\$ U1's DC power pins are fed through long paths, with no nearby smoothing capacitors. \$\endgroup\$
    – glen_geek
    Commented Jul 28, 2020 at 12:50
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    \$\begingroup\$ Why are you rebuilding that cheap board? If you need one, buy it, if not build what you do need. Incidentally, that is a terrible schematic. Connection via net labels has been standard practice for decades now and would make it possible to actually understand what is going on with the internals and the off board pins. \$\endgroup\$ Commented Jul 28, 2020 at 13:02
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    \$\begingroup\$ It seems like you have no filtering on VDDA and that you have violated all of the design guidelines for supply biasing with capacitors nowhere near their pin pairs. It's also entirely possible that either the MCU you are comparing to or the one you have sourced is a workalike and not an ST product. You may want to try swapping parts between boards. \$\endgroup\$ Commented Jul 28, 2020 at 13:04
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    \$\begingroup\$ Those "decoupling" caps C6-C10 are serving no purpose at all placed so far from the micro. There needs to be a cap right next to each pair of power pins on the micro. And please learn to use net names & buses when you draw your next schematic - this one is barely readable with all that spaghetti. That PCB was auto-routed wasn't it ... and no-one bothered to even clean up afterwards. \$\endgroup\$
    – brhans
    Commented Jul 28, 2020 at 13:37
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    \$\begingroup\$ One thing that's fairly clear from the picture is that properly supporting the chip with bypassing, etc between those through hole header rows while staying in a very budget process is going to be tricky. I seem to recall the actual bluepills having components on the bottom as well, but don't feel like digging one out. It may be that there's more subtle cleverness in making the blue pill actually work at barebones cost than is immediately apparent. But there's little reason to constrain your custom board with these challenges. Throw away that picture and shape and do a good design. \$\endgroup\$ Commented Jul 28, 2020 at 14:47

3 Answers 3


I agree with analogsystemsrf that the power supply of the MCU is the likely problem. But there are more problems than mentioned.

Have a look at Application Note AN2586 (Getting started with STM32F10xxx hardware development). It clearly outlines how the power supply should be designed. Several issues should be improved:

  • Decoupling capacitors should be close to each power supply pin of the MCU
  • Analog supply should have a separate set of decoupling capacitors
  • Both the analog and the digital supply should have an additional bigger capacitor (1µF or 4.7µF in addition to the several 100nF ones)
  • The board should have a ground plane
  • The AMS1117 output capacitor (1µF) is at the lower limit


As an example for a STM32F103C8 design with components on a single side only, see the below board.

I don't have the schematic or PCB layout but I'm quite confident the capacitors near the corners of the STM32 MCU are the decoupling capacitors. The component near the pins A2/A3 might even be a ferrite bead for the analog supply.

STM32F103C8 design

  • \$\begingroup\$ Thanks for your valuable comments.. 1. I have changed my schematic and layout as per comments 2. decoupling cap nearby MCU 3. separate GND layer for supply 4. All decoupling cap in the bottom layer layout attached below and check whether the layout is good for fabrication? [1]: i.sstatic.net/qLHmf.png \$\endgroup\$ Commented Jul 29, 2020 at 8:08

[I don't see a GROUND PLANE LAYER. If there is no such layer, then you need to add a GROUND PLANE.]

The ADC has a high_speed comparator (probably just a few nanoseconds needed to make a binary_search decision).

For that comparator to correctly "decide", the power supply needs to be stable.

However, with 10 milliMeters, or 20mm or 30mm, of PCB trace between the external Charge Reservoirs and the internal circuits, there will be lots of Inductive Kick (inductive Bounce) in the traces, and also magnetic coupling between VDD_Dig and VDD_Analog.

So you need to experiment, by soldering 0.1uF Surface_mount capacitors UNDER the MCU.


Thanks for your valuable comments..

  1. I have changed my schematic and layout as per comments
  2. decoupling cap nearby MCU
  3. separate GND layer for supply
  4. All decoupling cap in the bottom layer

layout attached below and check whether the layout is good for fabrication?

modified layout

  • \$\begingroup\$ Hi, You wrote this in the box labelled "Your Answer", but it isn't an answer (by Stack Exchange standards) as you are still asking questions - it's an update. Unlike typical internet forums, there are different places for answers and updates on Stack Exchange sites. (Please read the tour and help center to learn more.) Therefore please click "edit" below your question & add this as an update at the bottom of the existing question text (fix any duplicate image links). This "non-answer" will be flagged for deletion. You should move the update and then delete it from here yourself. Thanks. \$\endgroup\$
    – SamGibson
    Commented Jul 29, 2020 at 8:19

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