bjt diode analogy confusion

Question

I am studying bjts and one thing keeps me troubled. Bjts are shown as 2 diodes put together back to back but when I study this (let's say for npn), it is okay for base current flow to emitter as the diode between them is forward biased but I see that no current should flow from collector to emitter as there is diode which is reverse biased in between collector and base, which is on the way to emitter from collector. However, we get a current flow from collector to emitter anyways. Can you explain so that I can better understand Bjt circuits.

Answer 1

When the middle region, the base, is very very thin ( microns or less, in modern BJTs ), there is interaction between the forward-biased emitter_base junction and the reverse_biased collector_base junction.

What type of interaction? You might find this answer amusing. A guy with 10_year_old PhD in semiconductor_physics (in other words, lots of training and then 10 years experience and lots of time to discuss his evolving intuition with other people) explained the BJT behavior to me, like this:::::

"When the emitter_contributed carriers enter the base region, with the purpose of colliding with base_contributed carriers and CANCELLING the base carriers, MOST of the emitted carriers miss their targets and are very rapidly sucked over to the Collector region where there is a HIGH VOLTAGE GRADIENT."

Summary: the bipolar transistor depends on emitted carriers MISSING THEIR TARGETS almost all the time, and being collected in the collector.

The ratio of misses_to_hits is the very very useful BETA, which gives power gain to that mélange of junctions and dopings and external contacts we call a BJT.

Why is BETA important? Its basically the # of electrons OUT, per electron in.

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The challenge in the earliest BJT prototyping was achieving the extreme closeness between emitter and collector contacts, so their junctions could interact.

The first production BJTs were "point contact"; the base was a huge blob of doped silicon, with the Emitter and Collector being tiny regions thrown at the base material, with two tiny wires touching the Em and Col regions.

Eventually, the production houses discovered "planar" multi-layer fabrication.

However, one source of BJTs in modern semiconductor production is still the Point Contact, in the form of FETs and their underlying WELL.

The Source and Drain become the Emitter and Collector (often with no functional difference nor physical difference). The tub in which the FET was constructed is the WELL, and that is your base.

One horrid failure mechanism for semiconductors is "triggering the parasitic bipolar behavior", which means transient charges become high enough to turn on the "base region" and that turns on the collector current. This is called the BIPOLAR SNAPBACK failure.

I once had to diagnose a legacy FET IC in extremely high volume production [approaching 100,000,000 pieces a year] that would occasionally fail at various (undefined) conditions; the various users just returned the failed ICs with "It failed; we don't know why." And they would not discuss what they had changed, because "We've never had these fail before. That is why we buy this Part from your company." yet you knew the failures were in a new design with difference PCB layout and perhaps at higher clock rates, etc.

Turned out, under HIGH TRANSIENTS, mainly ringing on VDD pins with slewrate of 1volt/1nanosecond (or 1 Billion volts/second transient), the capacitively injected charges would ----- turn on the parasitic bipolars under the FETs.

Cure was to insert lots more "BASE" contacts, which we normally called "Well ties".

How did this happen? The ICs were characterized, decades prior, with DC_conditions. With DC_conditions, only leakage currents had to be gathered up by the Well ties, and sparse Well ties were adequate.

Took me about 3 months of fairly dedicated thinking, and staring at a Hanamatsu Recombination_Detection microscope, to realize the problem.

The trick was to find a way to "tickle the tail of the Dragon", to have the FETs enter the snapback behavior ---- but not self_destruct !! ---- and then have the circuit quench the snapback behavior so the localized heating would not destroy the FET under test, then do this again and again at high speed, so the microscope could produce photographs of the regions getting hot.