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\$\begingroup\$
module ram_reg;
parameter SIZE = 4;

reg [2:0] address;
reg [SIZE-1:0] data_in;
wire [7:0] connector;

reg clk;
reg rstn;
reg wr_rd;

output reg[SIZE-1:0] data_out; //LINE IN QUESTION
wire [SIZE-1:0] reg_out[7:0];


register #(SIZE) reg0 (.clk(clk), .data(data_in), .load(connector[0]), .rstn(rstn), .out(reg_out[0]));
register #(SIZE) reg1 (.clk(clk), .data(data_in), .load(connector[1]), .rstn(rstn), .out(reg_out[1]));
register #(SIZE) reg2 (.clk(clk), .data(data_in), .load(connector[2]), .rstn(rstn), .out(reg_out[2]));
register #(SIZE) reg3 (.clk(clk), .data(data_in), .load(connector[3]), .rstn(rstn), .out(reg_out[3]));
register #(SIZE) reg4 (.clk(clk), .data(data_in), .load(connector[4]), .rstn(rstn), .out(reg_out[4]));
register #(SIZE) reg5 (.clk(clk), .data(data_in), .load(connector[5]), .rstn(rstn), .out(reg_out[5]));
register #(SIZE) reg6 (.clk(clk), .data(data_in), .load(connector[6]), .rstn(rstn), .out(reg_out[6]));
register #(SIZE) reg7 (.clk(clk), .data(data_in), .load(connector[7]), .rstn(rstn), .out(reg_out[7]));

mux8 #(SIZE) mux_1 (.in0(reg_out[0]),.in1(reg_out[1]),.in2(reg_out[2]),.in3(reg_out[3]),.in4(reg_out[4]),.in5(reg_out[5]),.in6(reg_out[6]),.in7(reg_out[7]),.sel(address),.out(data_out));

//sevenSegment ss (.B(address), .segment(data_out));

up_counter uc (.clk(clk), .enable(wr_rd), .rstn(rstn));

endmodule

I am doing this in quartus, and it tells me "Top module port 'data_out' is not found in port list. The Quartus site just tells me Edit the design to make sure the port name appears in the list of ports in top-level module's Module Declaration, which I don't know how to do. I also tried writing it as just reg and just output and I get the same error.

\$\endgroup\$
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\$\begingroup\$

In the module declaration, you need to specify the port-list that are input/output.

module ram_reg(data_out);

Along with the declaration saying a particular reg/wire is input/output , we also need to specify them in port list. When you instantiate this module in any module, it interacts with these ports.

\$\endgroup\$

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