As part of a VLSI course I was asked to estimate the delay of an ALU, similar to the one described in the picture, using Logical Effort method.

I calculated the delay of the critical path through the ADD/SUB block, but I am not sure how the output capacitance of the multiplexer is calculated. Do I need to take into account all the blocks that enter the multiplexer in order to get the output capacitance needed to calculate the delay through ADD/SUB block only? Or can I just ignore the inactive blocks when calculating the delay of an active block?


Thank you


The logical effort of the entire gate is the ratio of its output logical effort to the sum of its input logical efforts. The answer depends on a schematics of your mux. It may happen that you need to consider all the signal paths within multiplexer.


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