I am using MABC-001000-DP000L, which is and Bias controller/sequencer. I am using this for Providing gate voltage and drain voltage to the power amplifier.

In the datasheet, it is mentioned that the module with combination of EVM can be used in two applications.

Application Option 1: Fixed negative gate biasing with pulsed drain biasing.

Application Option 2: Pulsed negative gate biasing with pulsed drain biasing.

I am trying to design both applications on a single board. The second option for future use.

For the 1st application option, he has mentioned a few pins as No connection and he has used those NC pins on the 2nd application.

enter image description here

The issue I am facing:-

They have used voltage followers for providing a low impedance output path for pin number 3(GCO). I have reverse-engineered the Ckt from the below-attached image, but I am unable to identify the voltage follower they have used.

Pin number 2 of the voltage follower has been connected to pin number 2 (NC/GCP) of the Module. There has been no description of this pin number.

I am guessing these:-

  1. Pin numbers 1 and 4 are connected together and output is provided through them.
  2. Pin number 5 is +Ve supply hence connected to GND(Highest +Ve supply)?
  3. Pin number 3 is connected to -8V
  4. Pin number 2 is connected to pin number 2 of MABC-001000-DP000L, which I am unable to understand.

I have mailed component manufacturer regarding full schematic, till now I haven't heard from them.

Can anybody help me with this?

Thanks in Advance.

Low-resolution pic of EVM. I don't think it helps in any way. enter image description here

Layout diagram

Layout Image


  • \$\begingroup\$ Specifically, what sort of help do you need? \$\endgroup\$
    – Andy aka
    Jul 29 '20 at 10:21
  • \$\begingroup\$ @Andyaka I would like to know the circuit diagram of the voltage follower, he has used. Can we guess the +V, -Ve supply pins and +Ve and -Ve input pins from the image? So that I can use another known voltage follower chip. \$\endgroup\$ Jul 29 '20 at 10:24
  • \$\begingroup\$ Is anything missing in my question, which is making others stop answering my question? \$\endgroup\$ Jul 30 '20 at 4:11
  • \$\begingroup\$ The question appears unanswerable in that if there was a circuit you'd post it but then you'd already know from the circuit what the voltage follower is. If there were pictures of a circuit board with the part on then surely you'd post those too. If the layout diagram you have posted contains the device in question surely you'd have put a pointer on that picture to the device in question. Basically, it seems inaccessible. \$\endgroup\$
    – Andy aka
    Jul 30 '20 at 7:37
  • \$\begingroup\$ @Andyaka I have marked the voltage follower on the layout image \$\endgroup\$ Jul 30 '20 at 7:42

Although your assumptions were wrong and the spec is correct, I found it hard at first to understand because of lack of details.

A full schematic, layout, and bill of materials are available upon request. Also, ask for details on an external layout for testing.

  1. Pin 1 & 3 are connected to DUT input as the voltage follower (internal Op Amp)
    Pin 4 is the non-inverting input. from VR1 from -8 Vdc .
    Pin 6 is TTL input pulses to drive Q1 Pch to pull up the DUT
    DUT is the QPA1022 4W 8.5 –11 GHz GaN Power Amplifier shown in Fig 1 for North Side bias. enter image description here
    enter image description here

  2. Pin 8 = Vds= 50V , Pin 7 = Gnd

  3. Pin 5 = -8V, Pin 7 = Gnd

enter image description here

  1. I see no evidence of pin 2 = NC connected to anything. (external only) Most likely a Test Pin. Perhaps why they said do not ground. Pin 6 is also NC but connected to pin 12, so I suppose those are interchangeable interconnects.
  • \$\begingroup\$ I received gerber data from MACOM support team. They have routed NC pins mentioned in pin configuration table. I have informed them. They said they will get back to me! \$\endgroup\$ Aug 6 '20 at 6:57
  • \$\begingroup\$ Did you try R testing that port with a DMM? It is likely an internal test point. \$\endgroup\$ Aug 6 '20 at 7:00
  • \$\begingroup\$ I will try testing with DMM. I asked them for schematic, but they are saying it is in datasheet. Do you think that Figure 1 is the complete schematic for Fixed gate and pulsed drain biasing? \$\endgroup\$ Aug 8 '20 at 9:16
  • \$\begingroup\$ It looks like it. \$\endgroup\$ Aug 8 '20 at 12:10
  • \$\begingroup\$ I received schematic from MACOM and i have added a snap of the same. They are not providing output gate voltage from pin number 1 and 3, in turn they have connected pin number 1 to pin number 2 and this is fed to voltage followers. \$\endgroup\$ Aug 12 '20 at 5:26

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