# Writing to a Register happens one or two clock cycles after asserting write enable?

I am using the code shown here Verilog: Writing to a Register Happens A Clock Cycle Late and that user posted a picture where output would change 2 cycles after asserting write enable. That post got an answer which seemed reasonably good to me. However, I decided to simulate the exact same code and create a testbench for it and in mine, output appears only 1 clock cycle after asserting write enable. Could somebody explain to me why is different if I'm doing the exact same thing?

The only difference I can spot is we're not using the same simulator but how could that be the reason?

This is testbench:

timescale 1ns / 1ps
module test_regblock_tb;

parameter tclk = 10;

reg clk = 1'b1;
reg rst = 1'b1;

always
#(tclk/2) clk =~clk;

initial begin
#(tclk*10);
rst = 1'b0;
end

reg [4:0] RegA_Name = 4'd5;
reg [4:0] RegB_Name = 4'd6;
reg [4:0] RegC_Name = 4'd7;
reg [31:0] RegA_In = 32'd0;
reg [31:0] RegC_In = 32'd0;
reg RegA_WrtEn = 1'b0;
reg RegC_WrtEn = 1'b0;

wire [31:0] RegA_Out;
wire [31:0] RegB_Out;

RegisterFile regblock(
.CLK(clk),
.RegA_Name(RegA_Name),
.RegB_Name(RegB_Name),
.RegC_Name(RegC_Name),
.RegA_In(RegA_In),
.RegC_In(RegC_In),
.RegA_WrtEn(RegA_WrtEn),
.RegC_WrtEn(RegC_WrtEn),
.RegA_Out(RegA_Out),
.RegB_Out(RegB_Out)
);

initial
begin
#(11*tclk);
RegA_In = 32'd126;
RegA_WrtEn = 1'b1;
#(tclk);
RegA_WrtEn = 1'b0;
#(50*tclk);
\$stop;

end

endmodule


The problem is with your testbench's use of #(tclk*N) followed by the use of blocking assignments to your design's inputs—it's a race condition. Your testbench should be using non-blocking assignments to any signals synchronized to the rising edge of tclk. Or you can adjust your testbench initial` block so that the signal changes do not coincide with the rising edge.