This is probably a simple question but how come CMOS Logic Gates built from Only Transistors is completely different from one that uses TTL Logic (Like BJT's). I know BJT aren't really used anymore because they consume power when they are "on" as compared to the low amount CMOS used.....but shouldn't the "Schematic" to produce a Gate be the same?
No, the circuit structures to produce gates in TTL and CMOS are very different.
It's actually a very complex topic, because at this level, you can't just treat transistors (BJTs or FETs) as simple "switches". It becomes an analog circuit design problem in which many issues need to be considered: how static and dynamic currents flow, where charges are stored on the various internal "nodes", connectivity among gates (fan-in and fan-out), etc.
Also, different types of transistor technology have different ways in which they can be applied. "True" TTL (74xx, 74Lxx, 74Hxx, 74Sxx) uses a single multi-emitter transistor to create a basic NAND structure with an arbitrary number of inputs; the rest of the circuitry is basically buffers so that the gate can drive the next gate(s) downstream.
LSTTL is really an advanced form of DTL (diode-transistor logic), in which the basic structure is an AND gate; again, the transistors are mainly for buffering.
In CMOS, the basic structure is a 2-transistor inverter. To create other logic functions, additional transistors are added in series/parallel with the original pullup/pulldown transistors of the inverter. Ideally, there is no static current draw at all, just the dynamic current of charging and discharging gate capacitances.
PMOS and NMOS were never offered as standardized gates in SSI/MSI packages, but these technologies were widely used in custom IC design for quite a while. The basic gate structure is basically half a CMOS gate, but with a passive pullup (a transistor used as a current source) as a load. All of the early microprocessor chips were built with these technologies.
Any technology based on MOS transistors has very high input impedances, which means that charge storage is a viable way of remembering data values, at least for short time periods. This can save a lot of transistors, and is why most early microprocessors had minimum as well as maximum clock frequencies. This technique can't be used with BJT technology.
There are tricks you can do with bipolar transistors that don't work the same way with MOSFETs, and vice-versa. For example, the TTL logic gates use transistors with multiple emitters in a common-base configuration as the input stage. But even then, the 74LS series logic used a different input circuit (a diode AND gate) for a different compromise between speed and power.
The multiple emitter trick doesn't transfer to FETs, but they have tricks of their own - depletion mode FETs can be made self-biasing, for example, so it is not surprising they use a different topology to achieve the same end.
Incidentally, CMOS logic in newer processes runs at lower voltages - so low that the transistors never quite turn fully off (subthreshold logic) - and their dimensions are so small that electrons can tunnel straight through - so now, CMOS is starting to consume power whether it is on or off...