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An ARM Cortex-M4 based microcontroller like TM4C123GH6PM is designed with multiple clock sources with a processor core clocked at 80MHz provided by the PLL, which, from what've read in NI-What is a PLL? and All About Circuit - What exactly is a PLL?, is some sort of feedback x oscillator circuitry that detects phase shift and stabilizes input frequencies through feedback. I don't understand how PLL relates to microcontroller. I'm not sensing any phase shift or trying to stabilize any signal here, and I don't get how the PLL magically produce a 400MHz clock.

Why is this PLL embedded in the microcontroller? If I want my processor to clock at max 80MHz as written in the specs then I just use an 80MHz external crystal. If some peripherals like USB require faster clock sources then I use a faster crystal and divide the clock to supply multiples of slower clock to other devices. External crystals are more accurate than internal oscillators anyway, so why bother stuffing a PLL in between an accurate external crystal and the processor, especially when I'm not dealing with any high frequency or RF application?

TM4C123 clock source

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  • \$\begingroup\$ Well, PLL is a feeback control technique which has nothing to do with MPU. As you can read from Wikipedia, PLL is used in many areas, include oscillator. Phase-locked loop - Wikipedia en.wikipedia.org/wiki/Phase-locked_loop. \$\endgroup\$ – tlfong01 Jul 31 at 2:13
  • \$\begingroup\$ I skimmed your two articles and found them explaining how PLL works. As I said, if you understand that PLL is used in oscillator circuits, then no question of why is it used in MCU, SBC or any other systems using an oscillator. But of course there is an exception, PLL is not as good an quartz/crystal, which is more precise, but more bulky and more expensive. \$\endgroup\$ – tlfong01 Jul 31 at 2:20
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    \$\begingroup\$ A 400MHz PLL driven by a 50MHz (or so) Xtal is not as accurate as a 400MHz Xtal (as tlfong01 points out too) but for many applications including MCU and consumer RF it's perfectly fine. Its versatility is a big plus, as well the ease of board/PCB routing it provides, as DKNguyen points out below in his answer. \$\endgroup\$ – P2000 Jul 31 at 3:00
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    \$\begingroup\$ Also have a look this article at analog.com/en/analog-dialogue/articles/… which I find more informative for the clock multiplication application in, for instamce, FPGAs \$\endgroup\$ – P2000 Jul 31 at 3:08
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    \$\begingroup\$ Designing a crystal oscillator that can operate in the range 4-8Mhz and a frequency multiplier that can multiply a frequency in that range by any value 1-16 (with a max of 80Mhz) is easier than designing a crystal oscillator that can operate efficiently at all frequencies in the range 4-80Mhz. \$\endgroup\$ – supercat Jul 31 at 17:10
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The PLL lets you be flexible with clock speed even after you've built the board, and of course, it lets you generate many different frequencies from the one onboard oscillator.

Honestly, just having a PLL so you can generate many frequencies off the onboard RC oscillator makes it worth having a PLL. That way you can operate flexibly with no external oscillator at all if you don't need one. From there, it's not too much more effort to make it so you can also re-route that PLL to an external oscillator.

The PLL lets you produce clocks faster than what is possible in a quartz crystal. Even though MEMS oscillators are available which can oscillate at much higher frequencies than quartz, you still might not want to operate directly off of one since a 400MHz external oscillator requires you to route a 400MHz trace.

As for how the PLL works. Do you know anything about music? Do you know how you can listen to a song and clap to the beat? You just keep equal timing between each clap and adjust the timing until each clap lands on a beat. Easy, right?

Now, do you know how you could do two, or even four claps per beat? A PLL does the same thing. You count your own claps and make sure the time between each clap is equal, but you adjust the time between claps until every fourth clap lands on the beat that you hear in the song, at which point you stop adjusting. In that way, you can produce a clap that is four times as fast even though the beat of the song is four time slower.

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    \$\begingroup\$ Thinking along this analogy, the PLL circuitry chases after the input frequency and output a constant 400MHz. So if I give it a 10MHz external crystal, the PLL will "clap" 80 times per crystal square wave period, and if it's a 25MHz, then the PLL will "clap" 16 times per period. Is this analogy correct to view the constant PLL output? \$\endgroup\$ – KMC Jul 31 at 4:44
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    \$\begingroup\$ @KMC Yes. Inside the PLL is a VCO. If too few cycles have passed in the time of one reference clock cycle, it speeds up the VCO a bit. If too many cycles have passed it decreases the frequency a bit by decreasing the control input. It keeps adjusting until the right number of cycles occur within one cycle of the reference clock. Theoretically, if the PLL suddenly loses the clock frequency it could be designed to still keep counting on its own but will gradually lose accuracy the same way you can keep clapping after the song ends or the beat disappears since the VCO isn't a good self-reference \$\endgroup\$ – DKNguyen Jul 31 at 4:52
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    \$\begingroup\$ @KMC Note there are analog PLLs that can work on sine-waves and digital PLLs which work on square waves. The VCO is always analog in both versions. It is the phase detector which can be digital or analog. \$\endgroup\$ – DKNguyen Jul 31 at 5:01
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    \$\begingroup\$ @DKNguyen, actually the phase slip between two clock signals is a continuous quantity: take XOR(clock1,clock2), if they align perfectly the output is all-zero. Now as you mis-align them, the XOR output exhibits pulses that get wider (not taller) per increasing phase difference. Low-pass-filter that (heavily) and you have an analog quantity proportionate to the phase difference. That goes into the VCO to increase/decrease its frequency. \$\endgroup\$ – P2000 Jul 31 at 5:46
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    \$\begingroup\$ This is a very good analogy! \$\endgroup\$ – Christian Lescuyer Aug 1 at 16:44
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I don't understand how PLL relates to microcontroller. I'm not sensing any phase shift or trying to stabilize any signal here, and I don't get how the PLL magically produce a 400MHz clock.

From the point of view of a microcontroller, a PLL is just a frequency multiplier. It takes some reference frequency like from a 10 MHz oscillator and generates all the other clock frequencies a microcontroller needs.

Why is this PLL embedded in the microcontroller? If I want my processor to clock at max 80MHz as written in the specs then I just use an 80MHz external crystal. If some peripherals like USB require faster clock sources then I use a faster crystal and divide the clock to supply multiples of slower clock to other devices.

Unless you happen to be able to find a single oscillator that can be divided down exactly to all the various frequencies you need, this usually isn't practical. Instead, you take a reference clock and multiply it up (or down) as needed. I have seen cheap devices that try to divide down a single clock, and it usually works really badly. They tend to have weird glitches, like producing 48kHz audio that sounds ok but 44.1kHz that runs fast since the LCM of 48000 and 44100 is a large number.

External crystals are more accurate than internal oscillators anyway, so why bother stuffing a PLL in between an accurate external crystal and the processor, especially when I'm not dealing with any high frequency or RF application?

In this case, the PLL uses an external oscillator, so provided it isn't incompetently implemented, it will be very accurate.

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To add to the other answers, there are couple of other reasons why a PLL may be useful:

To reduce EMC emissions (while also saving money, and reducing the chance of glitches)

To quote from ST application note AN1709:

Some microcontrollers have an embedded programmable PLL Clock Generator allowing the usage of standard 3 to 25 MHz crystals to obtain a large range of internal frequencies (up to a few hundred MHz). By these means, the microcontroller can operate with cheaper, medium frequency crystals, while still providing a high frequency internal clock for maximum system performance. The high clock frequency source is contained inside the chip and does not go through the PCB (Printed Circuit Board) tracks and external components. This reduces the potential noise emission of the application.

The use of PLL network also filters CPU clock against external sporadic disturbances (glitches).

To save power

In a low-power product, it can be very useful to have the option to run the processor (and its peripherals) at different speeds depending on what it needs to do at any point in time, or to generate assorted clocks at some times, but not others.

So this may involve increasing the clock speed when necessary, but decreasing it (or turning off the PLL altogether) at other times.

To give a concrete example: I worked on a battery-powered product which normally ran at 8 MHz, with the PLL off. However, periodically, we needed to generate much faster clocks to enable I2S streaming from an external audio chip. So, we spun up the PLL just for the few seconds where we needed those clocks, then shut it down when we were done.

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A PLL allows to multiply the frequency to a higher level than achievable with other means.

For instance, if there is a need to run a STM32 MCU at 400 MHz, there is no way to connect a 400 MHz crystal or square wave oscillator directly to a MCU.

A 4 MHz crystal can be used, and the PLL inside the MCU can be set to multiply the reference 4MHz by 100 to achieve 400 MHz clock for the MCU.

It can also be used runtime to change frequency if necessary to save power etc.

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This is not a microcontroller thing. Processors do this, various other products do this. On one side of it why waste the money on a high priced oscillator when you dont have to. Another side as mentioned is this gives you flexibility. What mcus have come to develop is an internal RC oscillator, add to that the PLL and you gain even more flexibility at a reduced cost if the accuracy is within your tolerance.

When you think of an X86 or an ARM based chip or whatever in part your cost savings but also you can keep the fast stuff mostly on die and have the outside stuff slower, so these chips are packed with PLLs, certainly the reference clock to 4Ghz or whatever your chip's main clock runs at but for the dram, pcie, network, etc you have plls that generate the various clocks for those various peripherals as not all of them run at the same speed. At times you have separate reference clocks for the various items (network, pcie, etc). So multiple oscillators/crystals depending.

How it magically makes a higher clock. Its a phase locked loop which you can google. It is basically an unstable analog circuit that oscillates, take some TTL logic, an odd number of inverters and tie them in a loop, if it happens to oscillate when they are powered, it will just keep oscillating. There is a non-zero amount of time for the signal coming in one side to invert and go out the other side, multiply that time by using more components, lowering the oscillating frequency at any one point (well one inverter and a bunch of non inverters). Buy boxes of components, and wire up multiple setups due to variations in the process, the connections, the power, etc no two sets will be identical, if they are momentarily one will drift relative to the other. Now harness this, intentionally create an unstable circuit like this (maybe not made of inverters but something that will oscillate) have a loose control as in vary the voltage it runs at and make it go faster and slower, then count oscillations. If I have a 100Mhz reference clock and want to make 400Mhz then I need to create a control system around the crappy oscillator to keep it counting 4 times for every 1 time the reference clock ticks. then use the output of the unstable oscillator as my 400Mhz clock. A lot of times you want to have the VCO (voltage controlled oscillator) or DCO, output be a higher frequency then divide that down to get your system/peripheral clock. For example easier to say multiply by 100 and then if you get a count of 99 speed up and a count of 101 slow down. Rather than say 2, if you get a count of 1 speed up a count of 3 slow down and the jitter being significantly larger. In the end there is no magic.

There was a time and were some products that you had to put an oscillator on. Today it doesnt make much sense, a lot of use cases are fine with the internal oscillator and its limited accuracy combined with the pll to provide various choices within one product and not requiring external non-free components. If a higher accuracy is required then there are quite often crystal and oscillator choices for the same product, not requiring the vendor to generate multiple chips that are otherwise the same just to deal with possible clocking choices.

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A uC has access to many configurable registers and counters which are useful for synthesizing a wide range of frequencies for many purposes.

A frequency mixer compares 2 clocks through a low pass filter to control a VCO which is used to derive one of the clocks. The other is from an internal RC oscillator or external very stable resonator with high Q. It may be a 32kHz tuning fork, MEMs, ceramic or quartz crystal resonator. Counters are used to scale the VCO but configured to either multiply or divide to achieve the result.

When the VCO counters are used as feedback to the mixer the VCO multiplies the fixed reference clock, but when used to feed-forward and divide down produces a lower f output. Fractional-N synthesizers use a combination of both.

The purposes of each clock are commonly known. CPU core, UART, I2C, Timer, etc.

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